MOTOROLA
Optimizing DSP56300/DSP56600 Applications
6-1
This section
describes various
Pipeline Interlocks
and suggests ways
to avoid them.
Section
6
PIPELINE INTERLOCKS
Due to the pipeline nature of the DSP56300 and DSP56600 Cores,
there are certain instruction sequences that cause a delay in
execution.
There are seven types of instruction sequence delays:
• External Bus Wait States
• External Bus Arbitration
• Instruction fetch delays
• Data ALU Pipeline Interlocks
• Address Generation Pipeline Interlocks
• Stack Extension delays
• Program flow Pipeline Interlocks
The first three types of instruction sequence delays can be avoided
by a better design of the overall memory system. If the main and
critical routines will be executed on-chip, both data movements and
instruction fetches, then the impact of these interlocks will be
negligible. However, it is very important for the user to be familiar
with and know ways to avoid those interlocks that are caused from
certain dependencies between instructions and operands.
Note:
The DSP56300 and DSP56600 assemblers generate a
warnings for every occurrence of a pipeline interlock. These
warnings help to locate places in the code where
optimization should be exercised to avoid interlocks. Also,
the reader is advised to read the
Appendix B
of the
DSP56300
and
DSP56600 Family Manuals
for detailed
description and definition of the various interlock and
pipeline delays.
6.1
DATA ALU PIPELINE INTERLOCKS
There are sequences related to Data ALU operation that cause the
insertion of one or two pipeline interlock cycles. This section
describes what are these sequences and suggests a few ways to
avoid them in the application.
