MOTOROLA
Optimizing DSP56300/DSP56600 Applications
B-1
This section
describes way to
optimize the
application for
minimal power
consumption.
Appendix
B
DEBUG AND TEST SUPPORT
The DSP56300 and DSP56600 families provide board and chip-level
testing capability through the On-Chip Emulation (OnCE) module
and the Test Access Port (TAP) commonly referred to as the JTAG
port. These two ports are both accessed through the JTAG port pins.
The DE pin is the only direct access to the OnCE module.
The presence of the JTAG interface allows the user to insert the DSP
chip into a target system while retaining debug control. This
capability is especially important for high speed devices, because it
eliminates the need for a costly cable to bring out the footprint of the
chip, as required by a traditional emulator system.
B.1
OnCE PORT FEATURES
The OnCE port is a Motorola-designed module used in DSP chips to
debug application software used with the chip. The port allows
non-intrusive interaction with the DSP and is accessible through the
pins of the JTAG interface. The OnCE module supports a special
debug environment that makes it possible to examine the contents
of registers, memory, or on-chip peripheral. This avoids sacrificing
other user-accessible on-chip resources to perform debugging. The
capabilities of the OnCE Port include:
• Generate Debug Event on a program memory address (fetch,
read, write or access)
• Generate Debug Event on a data memory address (read,
write, or access)
• Generate Debug Event on an on-chip peripheral register
access (read, write or access)
• Generate Debug Event using a special instruction
• Display/modify the contents of any DSP core register
• Display/modify the contents of any peripheral
memory-mapped registers
• Display/modify any desired sections of program or data
memory
