Motorola cm200 Commercial Series, Service Manual

Page: 82 / 352

2-20 THEORY OF OPERATION
9.2 Audio Processing and Digital Volume Control
The receiver audio signal (DISC AUDIO) enters the controller section from the IF IC where it is.DC
coupled to ASFIC CMP via the DISC input U504-pin 2. The signal is then applied to both the audio
and the PL/DPL paths
The audio path has a programmable amplifier, whose setting is based on the channel bandwidth
being received, an LPF filter to remove any frequency components above 3000 Hz, and a HPF to
strip off any sub-audible data below 300 Hz. Next, the recovered audio passes through a de-
emphasis filter (if it is enabled to compensate for Pre-emphasis which is used to reduce the effects
of FM noise). The IC then passes the audio through the 8-bit programmable attenuator whose level
is set depending on the value of the volume control. Finally the filtered audio signal passes through
an output buffer within the ASFIC CMP. The audio signal exits the ASFIC CMP at AUDIO output
(U504 pin 41).
The µP programs the attenuator, using the SPI BUS, based on the volume setting. The minimum /
maximum settings of the attenuator are set by codeplug parameters.
Since sub-audible signaling is summed with voice information on transmit, it must be separated
from the voice information before processing. Any sub-audible signaling enters the ASFIC CMP
from the IF IC at DISC U504-2. Once inside, it goes through the PL/DPL path. The signal first
passes through one of the two low-pass filters, either the PL low-pass filter or the DPL/LST low-pass
filter. Either signal is then filtered and goes through a limiter and exits the ASFIC CMP at LSIO
(U504-pin 18). At this point, the signal will appear as a square wave version of the sub-audible
signal which the radio received. The µP U403 pin 80 will decode the signal directly to determine if it
is the tone / code which is currently active on that mode.
9.3 Audio Amplification Speaker (+) Speaker (-)
The output of the ASFIC CMP’s digital volume pot, U504-pin 41 is routed through DC blocking
capacitor C5049 to the audio PA (U502 pin 1 and 9).
The audio power amplifier has one inverted and one non-inverted output that produces the
differential audio output SPK+/SPK- (U502 pins 4 and 6)
The audio PA is enabled via the ASFIC CMP (U504-GCB1). When the base of Q501 is low, the
transistor is off and U502-pin 8 is high, using pull up resistor R5041, and the audio PA is ON. The
voltage at U502-pin 8 must be above 8.5 Vdc to properly enable the device.
If the voltage is between 3.3 and 6.4 V, the device will be active but has its input (U502-pins 1/9) off.
This is a mute condition which is used to prevent an audio pop when the PA is enabled.
The SPK+ and SPK- outputs of the audio PA have a DC bias which varies proportionately with B+
(U502- pin 7). B+ of 11 V yields a DC offset of 5 V, and B+ of 17 V yields a DC offset of 8.5 V. If
either of these lines is shorted to ground, it is possible that the audio PA will be damaged. SPK+ and
SPK- are routed to the accessory connector (P1-pin 1 and 16) and to the control head (connector
J2-pins 19 and 20).