Motorola cm200 Commercial Series, Service Manual

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Controller Theory of Operation 2-11
While the radio is switched on, the µP monitors the voltage at the emergency input on the accessory
connector via U403-pin 62. Three different conditions are distinguished: no emergency kit is
connected, emergency kit connected (unpressed), and emergency press.
If no emergency switch is connected or the connection to the emergency switch is broken, the
resistive divider R5030 / R5049 will set the voltage to about 3.14 volts (indicates no emergency kit
found via EMERGENCY_SENSE line). If an emergency switch is connected, a resistor to ground
within the emergency switch will reduce the voltage on EMERGENCY _SENSE line, and indicate to
the µP that the emergency switch is operational. An engaged emergency switch pulls line
EMERGENCY _SENSE line to ground level. Diode VR503 limits the voltage to protect the µP input.
While EMERGENCY _ACCES_CONN is low, the µP starts execution, reads that the emergency
input is active through the voltage level of µP pin 64, and sets the DC POWER ON output of the
ASFIC CMP pin 13 to a logic high. This high will keep Q505 in saturation for soft turn off.
5.4 Microprocessor Clock Synthesiser
The clock source for the µP system is generated by the ASFIC CMP (U504). Upon power-up the
synthesizer IC (FRAC-N) generates a 16.8 MHz waveform that is routed from the RF section to the
ASFIC CMP pin 34. For the main board controller the ASFIC CMP uses 16.8 MHz as a reference
input clock signal for its internal synthesizer. The ASFIC CMP, in addition to audio circuitry, has a
programmable synthesizer which can generate a synthesized signal ranging from 1200 Hz to
32.769 MHz in 1200 Hz steps.
When power is first applied, the ASFIC CMP will generate its default 3.6864 MHz CMOS square
wave UP CLK (on U504 pin 28) and this is routed to the µP (U403 pin 90). After the µP starts
operation, it reprograms the ASFIC CMP clock synthesizer to a higher UP CLK frequency (usually
7.3728 or 14.7456 MHz) and continues operation.
The ASFIC CMP may be reprogrammed to change the clock synthesizer frequencies at various
times depending on the software features that are executing. In addition, the clock frequency of the
synthesizer is changed in small amounts if there is a possibility of harmonics of the clock source
interfering with the desired radio receive frequency.
The ASFIC CMP synthesizer loop uses C5025, C5024 and R5033 to set the switching time and jitter
of the clock output. If the synthesizer cannot generate the required clock frequency it will switch
back to its default 3.6864 MHz output.
Because the ASFIC CMP synthesizer and the µP system will not operate without the 16.8 MHz
reference clock it (and the voltage regulators) should be checked first when debugging the system.