Motorola cm200 Commercial Series, Service Manual

Page: 273 / 352

Controller Theory of Operation 2-13
5.8 Normal Microprocessor Operation
For this radio, the µP is configured to operate in one of two modes, expanded and bootstrap. In
expanded mode the µP uses external memory devices to operate, whereas in bootstrap operation
the µP uses only its internal memory. In normal operation of the radio the µP is operating in
expanded mode as described below.
During normal operation, the µP (U403) is operating in expanded mode and has access to 3
external memory devices; U400 (EEPROM), U402 (SRAM), U404 (Flash). Also, within the µP there
are 3 Kilobytes of internal RAM, as well as logic to select external memory devices.
The external EEPROM (U400) space contains the information in the radio which is customer
specific, referred to as the codeplug. This information consists of items such as: 1) what band the
radio operates in, 2) what frequencies are assigned to what channel, and 3) tuning information.
The external SRAM (U402) as well as the µP’s own internal RAM space are used for temporary
calculations required by the software during execution. All of the data stored in both of these
locations is lost when the radio powers off.
The µP provides an address bus of 16 address lines (ADDR 0 - ADDR 15), and a data bus of 8 data
lines (DATA 0 - DATA 7). There are also 3 control lines; CSPROG (U403-38) to chip select U404-pin
30 (FLASH), CSGP2 (U403-pin 41) to chip select U404-pin 20 (SRAM) and PG7_R_W (U403-pin 4)
to select whether to read or to write. The external EEPROM (U400-pin1).
When the µP is functioning normally, the address and data lines should be toggling at CMOS logic
levels. Specifically, the logic high levels should be between 3.1 and 3.3 V, and the logic low levels
should be between 0 and 0.2 V. No other intermediate levels should be observed, and the rise and
fall times should be <30 ns.
The low-order address lines (ADDR 0 - ADDR 7) and the data lines (DATA 0-DATA 7) should be
toggling at a high rate, e.g., you should set your oscilloscope sweep to 1us/div. or faster to observe
individual pulses. High speed CMOS transitions should also be observed on the µP control lines.
On the µP the lines XIRQ (U403-pin 48), MODA LIR (U403-pin 58), MODB VSTPY (U403-pin 57)
and RESET (U403-pin 94) should be high at all times during normal operation. Whenever a data or
address line becomes open or shorted to an adjacent line, a common symptom is that the RESET
line goes low periodically, with the period being in the order of 20ms. In the case of shorted lines you
may also detect the line periodically at an intermediate level, i.e. around 2.5 V when two shorted
lines attempt to drive to opposite rails.
The MODA LIR (U403-pin 58) and MODB VSTPY (U403-pin 57) inputs to the µP must be at a logic
“1” for it to start executing correctly. After the µP starts execution it will periodically pulse these lines
to determine the desired operating mode. While the Central Processing Unit (CPU) is running,
MODA LIR is an open-drain CMOS output which goes low whenever the µP begins a new
instruction. An instruction typically requires 2-4 external bus cycles, or memory fetches.
There are eight analog-to-digital coverter ports (A/D) on U403 labelled within the device block as
PEO-PE7. These lines sense the voltage level ranging from 0 to 3.3 V of the input line and convert
that level to a number ranging from 0 to 255 which is read by the software to take appropriate action.