
RX SIGNAL PATH
TX SIGNAL PATH
MAIN VCO SIGNAL PATH
TUNING VOLTAGES
REFERENCE CLOCK
ADDRESS BUS
RF TRANSCEIVER SPI
to RF Transceiver U200
RX_ACQ
RX_EN
TX_KEY
DM_CS
TX_EN
CLK_SELCT
RESET
A1
C1
E2
E1
E3
E4
-5V
DP_EN_L
KBR0, KBR2
KBC0, KBC1, KBC2
V1
SIMPD0
DEEP SLEEP
2
1
P2
LS1_IN
LS2_IN
SIM_TX
SIM_RX
( SDTX ) BDX
( TX_CLK ) BCLKX
from/to MAGIC
BCLKR
( SDFS ) BFSR
( SDRX ) BDR
STBY_DL
CIRCUIT
V1
V2
VREF
V1_SW
U800
CALL PROCESSOR
SPI
INTERFACE
TIMER
SPI
INTERFACE
H10
P4
J1
A4
A11
H2, H1, H3
J5, J3, J2
UART
INTERF.
INTERFACE
M
E
M
O
R
Y
I
N
T
E
R
F
A
C
E
E9
E7
F3
B5
SIM
INTER
FACE
CTM
MODULE
DSC
SERIAL
INTER
FACE
DSP
CHARGE
UART
CPU
B6
B3
B4
D4
A3
F1
V2
V3
C14, F10, G4, H4, K5, P13
A9, A10, C5, K6, K10, M8, M11
B7
HEAD_INT_L
U904
U903
4
-10V
1
P2
U900
GCAP II
J600
MAIN ACCESSORY CONN.
CON.
H6 H7
H9
SENSE
CNTL.
MAN_TEST_AD
DSC_EN_AD
DOWNLINL_AD
BATT_THERM_AD
ISENSE
A1
B2
A2
B3
D9
REAL TIME
CLOCK
Y
9
0
0
A7 B7
3
2
.7
6
8
K
H
z
SPR-
SPR+
REG.
V2
REG.
V3
REG.
VBOOST1
REG.
L901
B+
V_BOOST1
V1
V2
V3
VREF
REG.
VREF
2.775V, for Call processor logic outputs, RAM, FLASH, EEPROM
1,8V, for Call Processor
VSIM
REG.
VSIM1
V1
5.0V, for DSC Bus, Negative Voltage Regulator
Internal GCap use only (VSIM1, LS_V1)
3.0 or 5.0V, for SIM Card Circuit
P
A
_
D
R
V
RESET
2.775V,for RF Transceiver
K6
E18
B10
J5
C6
B5
G9
A6
A10, C10
C7
EXT_B+
14
1
3
10
5
RS232_TX
RS232_RX
6
7
DSC_EN
13
12
11
UPLINK
DOWNLINK
GND
GND
GND
M
A
G
IC
_
1
3
M
H
z
G
C
L
K
SIM_CLK
SIM_RST
SIM_I/O
LEVEL
PWR_SW
C8
K7
G6
K10
LS1_IN
LS2_IN
SIM_TX
SIM_RX
H8
SHIFT
A5
A6
K2
J504
HEAD_INT_L
J2
Q938
J9
CR902
F6
J8
J7
Logic Control
A
U
D
IO
S
P
I
G
C
A
P
S
P
I
D2
C2
R
T
C
_
B
A
T
T
D6
HEADSET
STBY_DL
G4
C4
G
C
A
P
_
C
L
K
1
3
M
H
z
F5
EXT_B+
Audio
Codec
Interface
SPI
INTERFACE
15
GND
G5
ON/OFF
9
SW_RF
8
2
EXT_CHG_EN
CHRGC
E4
E3
E1
E2
C1
A1
N3
V2
C2
WC_~RTS1
R976
R977
4
1-3
5-8
ON_2
K1
VIB_EN
C5, B6
A5
U905, Q908
THERM
B+
BATT+
EXT_B+
BATT_FDBK
BATT_SER_DATA
STBY_DL
U702
U701
SRAM
FLASH
V2
SR_VCC
CE0
CE1
CE2
CE3
R_W
A4, E1, F5
D7
F8
C9
E10
D9
B9
RESET
E1
SR_VCC
R_W
B3
B11
B4
B2
IrDA_EN
DATA BUS
VDDS
VCC_MEMIF
VDD
VCCA
H5
CR903
Q901
1
6,8
Q902
L1
CHRG_EN
Q900
R
9
1
3
3
4
E8
B+
U703
SRAM
SR_VCC
CE8
R_W
CE8
C11
A6
B5
G5
G5
B2
A6
A1
TP 878
C913
BATT+
Q600
RS232EN/EXT_CHG_EN
Multiplexer
DB_~CTS
BATT_FDBK
WC_URXD1
WC_UTXD1
4
BOOM_EN
DB_~RTS
U907
SPST
DB_URXD
DB_UTXD
MIC+
MIC-
1
2
5
4
3
6
SIM2_PD
K4
SIM2_RST
SIM2_CLK
M1
L3
battery detect
SMART
VOL_UP
VOL_DOWN
KBC1
KBR0
KBR3
KBC0
KBC2
KBC0
KBC3
to ~DW_INT
Q904
Q905
Q909
5
2
MAIN_FET
F10
4
6,4
MIDRATE_2
EXT_B+
R917
SEND/END DETECT
V22
V2
Q2121
KBR0
Q2122
KBR3
U908
R2489
R2491
AUX_MIC
AUX_MIC
MIC_BIAS
H3
STBY DELAY
U906,CR912
STBY_PCS
CIRCUIT
Q911,Q912,Q913
7,8
4
1,2
5,6
4
3
2
L7
MIDRATE_1
L6
4
2
3
R2488
BATT+
Q907
BACK UP
BATTERY
2
1
1
6
4
5
SWITCH
SILENT LED
Q505
LED_RED
LED_GREEN
5
2
3
6 4
CIRCUIT
CR500
1
2
4
3
RED
GREEN
2
3
Q810
1
2
DOWNLINK
DETECT
J905
2
1
R508
3
CR905
ON_2
DB_~CTS/
32MBIT
2MBIT
2MBIT
A7
C7
E8
C8
A8
B8
D8
EMU1
TCK
TRST*
TDI
TMS
EMU0
TDO
TP810
TP817
TP816
TP812
TP811
TP813
TP815
TP809
V2
TP814
JTAG
P900
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
BATT+
BATT+
CONTL. SIGNAL
TRANC. SIGNAL
BATT+
BATT+
BATT+
BATT+
BATT+
BATT+
BATT+
BATT+
BATT+
BATT+
BATT+
BATT+
BATT+
BATT+
SIM2_RST
SIM2_RST
SIM2_PD
SIM2_PD
V_BOOST1_REG
V_BOOST1_REG
SIM2_CLK
SIM2_CLK
SIM2_IO
SIM2_IO
BATT_SER_DATA
BATT_SER_DATA
GND
GND
GND
GND
THERM
THERM
VSIM
VSIM1
~
RTS1
DB_
~
RTS
SIM_RST
SIM_RST
~
CTS1
DB_
~
CTS
SIM_CLK
SIM_CLK
URXD1
DB_URXD
SIM_IO
SIM_IO
UTXD1
DB_UTXD
XCVR_PWR
XCVR_PWR
AUX_MIC
AUX_MIC
MIC+
MIC+
MIC-
MIC-
~
DCABLE_INT
DCABLE_INT
SPKR_OUT
(NC)
SPKR-
~
DW_INT
~
DW_INT
DBRTS_WCCTS
WC_
~
CTS1
~
WD_INT
~
WD_INT
DBCTS_WCRTS
WC_
~
RTS1
GCAP_V2
V2
DBRX_WCTX
WC_UTXD1
WC_
~
RESET
RESET
DBTX_WCRX
WC_URXD1
B+
B+
B+
B+
HEAD_DET
HEAD_DET
HEAD_INT_L
HEAD_INT_L
(to Q907)
(from P900)
MIC_BIAS
R957
~DCABLE_INT
DCABLE_INT
N1M2 N2
N6
V2
(to Antenna Switch)
CHARGE
SENSE
E18 F7
(f
ro
m
U
2
0
0
)
EEPROM
One Wire
KEYBOARD
XCVR_PWR
BATT_FDBK
S523
S508
S512
(UART1)
RS232 EXT.
to/from Q600,
J600 and U907
(UART2)
Interprocessor
Comunication
between U800
and U001
(from/ to P900)
A009 - TRANSCEIVER BLOCK DIAGRAM - PAGE
2
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