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Hardware Preparation

2-3

2

MVME162LX embedded controllers are factory tested and shipped
with the default configurations listed above and described in the
following sections. The MVME162LX’s required and factory-
installed debug monitor, MVME162Bug (162Bug), operates with
those factory settings.

System Controller Select Header (J1)

The MVME162LX is factory-configured as a VMEbus system
controller by a jumper across J1 pins 1 and 2. If you select the
‘‘automatic’’ system controller function by moving the jumper to J1
pins 2 and 3, the MVME162LX determines whether it is the system
controller by its position on the bus. If the board is in the first slot
from the left, it configures itself as the system controller. If the
MVME162LX is not to be system controller under any
circumstances, remove the jumper from J1. When the board is
functioning as system controller, the

SCON

LED is turned on.

Note

For MVME162LXs without the optional VMEbus
interface (i.e., with no VMEchip2), the jumper may be
installed or removed without affecting normal
operation.

1

2

3

1

2

3

J1

1

J1

Not system controller

2

3

J1

Auto system controller

System Controller

(Factory

Configuration)

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Summary of Contents for 700 Series

Page 1: ...700 800 Series MVME162LX Embedded Controller Installation and Use 700 800 Series MVME162LX Embedded Controller Installation and Use ...

Page 2: ......

Page 3: ...700 800 Series MVME162LX Embedded Controller Installation and Use V162 7A IH1 ...

Page 4: ...r written permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not announced in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Restricted Rights L...

Page 5: ...ng the firmware on the MVME162LX VME Embedded Controller This manual is intended for anyone who wants to design OEM systems supply additional capability to an existing compatible system or work in a lab environment for experimental purposes A basic knowledge of computers and digital logic is assumed Companion publications are listed beginning on page 1 3 Assembly Item Board Description Assembly It...

Page 6: ...l or other qualified maintenance personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Do not replace components with the power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and discharge circuits before touching them Do Not Service or Adj...

Page 7: ... manufacturer s instructions Attention Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du même type ou d un type équivalent recommandé par le constructeur Mettre au rebut les batteries usagées conformément aux instructions du fabricant Vorsicht Explosionsgefahr bei unsachgemäßem Austausch der Batterie Ersatz nur durch denselben oder e...

Page 8: ...All other products mentioned in this document are trademarks or registered trademarks of their respective holders Copyright Motorola 1997 All Rights Reserved Printed in the United States of America October 1997 European Notice Board products with the CE marking comply with the EMC Directive 89 336 EEC Compliance with this directive implies conformity to the following European Norms EN55022 CISPR 2...

Page 9: ...ture Operation 1 9 FCC Compliance 1 11 Manual Terminology 1 11 Block Diagram 1 13 Functional Description 1 13 Front Panel Switches and Indicators 1 13 Data Bus Structure 1 15 Microprocessor 1 15 MC68040 Cache 1 15 No VMEbus Interface Option 1 16 Memory Options 1 16 DRAM Options 1 16 SRAM Options 1 17 About the Battery 1 18 EPROM and Flash Memory 1 20 Battery Backed Up RAM and Clock 1 20 VMEbus Int...

Page 10: ... Memory Map 1 33 Chapter 2 Hardware Preparation and Installation Introduction 2 1 Unpacking Instructions 2 1 Hardware Preparation 2 1 System Controller Select Header J1 2 3 IP Bus Clock Header J11 2 5 SCSI Terminator Enable Header J12 2 6 SRAM Backup Power Source Select Header J14 2 6 Flash Write Protect Header J16 2 7 IP Bus Strobe Select Header J18 2 8 IP DMA Snoop Control Header J19 2 8 EPROM F...

Page 11: ... Sectors 3 15 Device Probe Function 3 16 Disk I O via 162Bug Commands 3 16 IOI Input Output Inquiry 3 16 IOP Physical I O to Disk 3 16 IOT I O Teach 3 17 IOC I O Control 3 17 BO Bootstrap Operating System 3 17 BH Bootstrap and Halt 3 17 Disk I O via 162Bug System Calls 3 17 Default 162Bug Controller and Device Parameters 3 19 Disk I O Error Codes 3 19 Network I O Support 3 19 Intel 82596 LAN Copro...

Page 12: ...Offset Registers 4 7 Port Numbers 4 9 Entering and Debugging Programs 4 9 Creating a Program with the Assembler Disassembler 4 10 Downloading an S Record Object File 4 10 Read the Program from Disk 4 10 Calling System Utilities from User Programs 4 11 Preserving the Debugger Operating Environment 4 11 162Bug Vector Table and Workspace 4 12 Examples 4 12 Hardware Functions 4 13 Exception Vectors Us...

Page 13: ...he IndustryPacks A 14 Appendix B Disk Tape Controller Data Disk Tape Controller Modules Supported B 1 Disk Tape Controller Default Configurations B 2 IOT Command Parameters for Supported Floppy Types B 4 Appendix C Network Controller Data Network Controller Modules Supported C 1 Appendix D Troubleshooting CPU Boards Solving Startup Problems D 1 ...

Page 14: ... 1 28 Table 1 5 Local I O Devices Memory Map 1 30 Table 2 1 Jumper Settings 2 2 Table 2 2 J19 Snoop Control Encoding 2 9 Table 2 3 EPROM Flash Mapping 256K x 8 EPROMs 2 11 Table 2 4 EPROM Flash Mapping 512K x 8 EPROMs 2 11 Table 2 5 EPROM Flash Mapping 1M x 8 EPROMs 2 11 Table 2 6 EPROM Flash Mapping 1M x 8 EPROMs Onboard Flash Disabled 2 12 Table 2 7 Memory Mezzanine Stacking Options 2 14 Table 4...

Page 15: ... microprocessor Various versions of the MVME162LX have parity protected DRAM 4MB 8M or 16MB or ECC protected DRAM 4MB 8MB 16MB or 32MB 128KB of SRAM with battery backup a time of day clock with battery backup an optional LAN Ethernet transceiver interface four serial ports with EIA 232 D interface six tick timers with watchdog timer s two EPROM sockets 2MB Flash memory one Flash device two Industr...

Page 16: ...ss interface a VMEbus interrupter a VMEbus system controller a VMEbus interrupt handler and a VMEbus requester Processor to VMEbus transfers are D8 D16 or D32 VMEchip2 DMA transfers to the VMEbus however are D16 D32 D16 BLT D32 BLT or D64 MBLT MC2chip Provides four tick timers the interface to the LAN chip SCSI chip serial port chip BBRAM EPROM Flash parity DRAM and SRAM MCECC memory controller Pr...

Page 17: ...ou can contact Motorola for this purpose in several ways Through your local Motorola sales office Through the World Wide Web site listed on the back cover of this and other MCG manuals USA and Canada only By contacting the Literature Center via phone or fax at the numbers listed under Product Literature at MCG s World Wide Web site If any supplements have been issued for a manual or guide they wil...

Page 18: ...o the 700 800 series MVME162LX and may provide additional helpful information They may be purchased through your local Motorola sales office Motorola Publication Number Description MVME162LXPG D MVME162LX Embedded Controller Programmer s Reference Guide MVME162BUG D MVME162Bug Debugging Package User s Manual 68KBUG1 D 68KBUG2 D Debugging Package for Motorola 68K CISC CPUs User s Manual Parts 1 and...

Page 19: ...Revision 10c Global Engineering Documents 15 Inverness Way East Englewood CO 80112 5704 82596CA Local Area Network Coprocessor Data Sheet order number 290218 and 82596 User s Manual order number 296853 Intel Corporation Literature Sales P O Box 58130 Santa Clara CA 95052 8130 28F016SA Flash Memory Data Sheet order number 290435 Intel Corporation Literature Sales P O Box 7641 Mt Prospect IL 60056 7...

Page 20: ... 0 order number ANSI VITA 4 1995 VITA VMEbus International Trade Association 7825 E Gelding Dr Ste 104 Scottsdale AZ 85260 3415 Z85230 Serial Communications Controller Data Sheet Zilog Inc 210 Hacienda Ave Campbell CA 95008 6609 Table 1 1 700 800 Series MVME162LX Features Feature Description Microprocessor 32MHz MC68040 DRAM mezzanine 4 8 16MB with parity protection or 4 8 16 32MB with ECC protect...

Page 21: ...our serial ports with EIA 232 D interface serial port controllers are the Z85230 chips SCSI I O Optional SCSI Bus interface with DMA Ethernet I O Optional Ethernet transceiver interface with DMA IndustryPack I O Two IP interfaces with two channel DMA VMEbus interface VMEbus system controller functions VMEbus interface to local bus A24 A32 D8 D16 D32 block transfer D8 D16 D32 D64 Local bus to VMEbu...

Page 22: ...ximum Operating temperature 0 to 70 C exit air with forced air cooling see Note Storage temperature 40 to 85 C Relative humidity 5 to 90 noncondensing Physical dimensions PC board with mezzanine module only Height Depth Thickness PC board with connectors and front panel Height Depth Thickness Double high VMEboard 9 2 inches 233 mm 6 3 inches 160 mm 0 66 inch 17 mm 10 3 inches 262 mm 7 4 inches 188...

Page 23: ...ons Case temperatures of critical high power density integrated circuits are monitored to ensure that component vendors specifications are not exceeded While the exact amount of airflow required for cooling depends on the ambient air temperature and the type number and location of boards and other heat sources adequate cooling can usually be achieved with 10 CFM and 490 LFM flowing over the contro...

Page 24: ... The chassis was placed in a thermal chamber that maintained an ambient temperature of 55 C Measurements showed that the fans in the chassis supplied an airflow of approximately 65 LFM over the MVME172 boards Under these conditions a rise in temperature of approximately 10 C between the inlet and exit air was observed The junction temperatures of selected high power devices on the MVME172 were cal...

Page 25: ... 3 Conductive chassis rails connected to earth ground This provides the path for connecting shields to earth ground 4 Front panel screws properly tightened For minimum RF emissions it is essential that the conditions above be implemented Failure to do so could compromise the FCC compliance of the equipment containing the module Manual Terminology Throughout this manual a convention is used which p...

Page 26: ...t significant A two byte is 16 bits numbered 0 through 15 with bit 0 being the least significant For the MVME162LX and other CISC modules this is called a word A four byte is 32 bits numbered 0 through 31 with bit 0 being the least significant For the MVME162LX and other CISC modules this is called a longword The terms control bit status bit true and false are used extensively in this document The...

Page 27: ...led by software ABORT switch When enabled by software the ABORT switch generates an interrupt at a user programmable level It is normally used to abort program execution and return to the 162Bug debugger FAIL LED red Lights when the BRDFAIL signal line is active or when the processor is halted Part of DS1 RUN LED green or amber Lights when the local bus TIP signal line is low This indicates one of...

Page 28: ...p 128KB SRAM Memory Array w Battery M48T58 Battery Backed 8KB RAM Clock 4 8 16 32MB Memory Array 4 8 16MB Parity DRAM Memory Array MPU VMEbus A32 24 D64 32 16 08 Master Slave IndustryPack I O 2 Channels Optional Ethernet Transceiver DB 15 Front Panel Connector SCSI Peripherals 68 pin Front Panel SCSI Connector Optional Optional 4 Serial Ports RJ 45 Front Panel EIA 232 Transceivers 21009702 Optiona...

Page 29: ...ssor The MVME162LX is built with a 32MHz MC68040 microprocessor The MC68040 has on chip instruction and data caches optional high drive I O buffers and a floating point processor The MC68040 supports cache coherency in multi master applications with dedicated on chip bus snooping logic Refer to the M68040 reference manual for detailed information MC68040 Cache The MVME162LX local bus masters VMEch...

Page 30: ... without the VMEbus interface are shipped with Flash memory blank the factory uses the VMEbus to program the Flash memory with debugger code To use the 162Bug package MVME162Bug be sure that jumper header J21 is configured for the EPROM memory map Refer to Chapters 2 and 3 for further details Contact your local Motorola sales office for ordering information Memory Options The following memory opti...

Page 31: ...ptions The MVME162LX provides 128KB of 32 bit wide onboard static RAM in a single non interleaved architecture with onboard battery backup The SRAM arrays are not parity protected The SRAM battery backup function is provided by a Dallas DS1210S device The DS1210S supports primary and secondary power sources When the main board power fails the DS1210S selects the source with the higher voltage If o...

Page 32: ...source for the onboard SRAM is a RAYOVAC FB1225 battery with two BR1225 type lithium cells which is socketed for easy removal and replacement A small capacitor is provided to allow the battery to be quickly replaced without data loss The lifetime of the battery is very dependent on the ambient temperature of the board and the power on duty cycle The lithium battery supplied on the MVME162LX should...

Page 33: ... If lithium batteries are mistreated or handled incorrectly they may burst open and ignite possible resulting in injury and or fire When dealing with lithium batteries carefully follow the precautions listed below in order to prevent accidents Do not short circuit Do not disassemble deform or apply excessive pressure Do not heat or incinerate Do not apply solder directly Do not use different model...

Page 34: ...tection memory write protection 8KB of RAM and a battery in one 28 pin package The clock provides seconds minutes hours day date month and year in BCD 24 hour format Corrections for 28 29 leap year and 30 day months are automatically made No interrupts are generated by the clock Although the M48T58 is an 8 bit device the interface provided by the MC2chip supports 8 16 and 32 bit accesses to the M4...

Page 35: ...ial communications interfaces Each interface supports CTS DCD RTS and DTR control signals as well as the TXD and RXD transmit receive data signals Because the serial clocks are omitted in the MVME162LX implementation serial communications are strictly asynchronous The MVME162LX hardware supports serial baud rates of 110b s to 38 4Kb s The Z85230 supplies an interrupt vector during interrupt acknow...

Page 36: ...programmed to access the VMEbus Therefore the 82596CA should not be programmed to access the VMEbus Every MVME162LX that has the Ethernet interface is assigned an Ethernet Station Address The address is 08003E2XXXXX where XXXXX is the unique 5 nibble number assigned to the board i e every MVME162LX has a different value for XXXXX Each board has an Ethernet Station Address displayed on a label atta...

Page 37: ...r s guide and to the MC2chip description in the MVME162LX Embedded Controller Programmer s Reference Guide for detailed programming information SCSI Termination It is important that the SCSI bus be properly terminated at both ends The MVME162LX main board provides terminators for the SCSI bus The SCSI terminators are enabled disabled by a jumper on header J12 If the SCSI bus ends at the MVME162LX ...

Page 38: ...d in both the MC2chip and the optional VMEchip2 The timers operate independently but in parallel When the watchdog timers are enabled they must be reset by software within the programmed time or they will time out The watchdog timers may be programmed to generate a SYSRESET signal local reset signal or board fail signal if they time out Refer to the VMEchip2 and MC2chip descriptions in the MVME162...

Page 39: ... µsec 64 µsec 256 µsec or infinity The local bus timer does not operate during VMEbus bound cycles VMEbus bound cycles are timed by the VMEbus access timer and the VMEbus global timer Refer to the VMEchip2 and the MC2chip descriptions in the MVME162LX Embedded Controller Programmer s Reference Guide for detailed programming information The MC2chip also provides local bus timeout logic for MVME162L...

Page 40: ... functions to be extended to the control panel of the system where they are visible The serial ports on the MVME162LX are connected to four 8 pin RJ 45 female connectors J17 on the front panel The two IPs connect to the MVME162LX by two pairs of 50 pin connectors Two 50 pin connectors behind the front panel are for external connections to IP signals The memory mezzanine board is plugged into two 1...

Page 41: ...MEbus masters Local Bus Memory Map The local bus memory map is split into different address spaces by the transfer type TT signals The local resources respond to the normal access and interrupt acknowledge codes Normal Address Range The memory map of devices that respond to the normal address range is shown in the following tables The normal address range is defined by the Transfer Type TT signals...

Page 42: ... Cache Inhibit Notes Programmable DRAM on parity mezzanine D32 4MB 16MB N 2 Programmable DRAM on ECC mezzanine D32 4MB 32MB N 2 Programmable Onboard SRAM D32 128KB N 2 Programmable VMEbus A32 A24 D32 D16 4 Programmable IP_a memory D32 D8 64KB 8MB 2 4 Programmable IP_b memory D32 D8 64KB 8MB 2 4 FF800000 FF9FFFFF Flash EPROM D32 2MB N 1 5 FFA00000 FFBFFFFF EPROM Flash D32 2MB N 5 FFC00000 FFDFFFFF ...

Page 43: ...er to the EPROM Flash configuration tables in the MVME162LX Embedded Controller Programmer s Reference Guide for further details 2 This area is user programmable The DRAM and SRAM decoder is programmed in the MC2chip the local to VMEbus decoders are programmed in the VMEchip2 and the IP memory space is programmed in the IP2 3 Size is approximate 4 Cache inhibit depends on the devices in the area m...

Page 44: ...3 FFF40100 FFF401FF VMEchip2 GCSR D32 D8 256B 1 3 FFF40200 FFF40FFF Reserved 3 5KB 4 5 FFF41000 FFF41FFF Reserved 4KB 4 FFF42000 FFF42FFF MC2chip D32 D8 4KB 1 FFF43000 FFF430FF MCECC 1 D8 256B 1 8 FFF43100 FFF431FF MCECC 2 D8 256B 1 8 FFF43200 FFF43FFF MCECCs repeated 3 5KB 1 5 8 FFF44000 FFF44FFF Reserved 8KB 4 FFF45000 FFF457FF SCC 1 Z85230 D8 2KB 1 2 FFF45800 FFF45FFF SCC 2 Z85230 D8 2KB 1 2 FF...

Page 45: ...6B 7 FFF58800 FFF5887F Reserved 128B 1 FFF58880 FFF588FF Reserved 128B 1 FFF58900 FFF5897F Reserved 128B 1 FFF58980 FFF589FF Reserved 128B 1 FFF58A00 FFF58A7F Reserved 128B 1 FFF58A80 FFF58AFF Reserved 128B 1 FFF58B00 FFF58B7F Reserved 128B 1 FFF58B80 FFF58BFF Reserved 128B 1 FFF58C00 FFF58CFF Reserved 256B 1 FFF58D00 FFF58DFF Reserved 256B 1 FFF58E00 FFF58EFF Reserved 256B 1 FFF58F00 FFF58FFF Res...

Page 46: ...ignal Writes to the GCSR may be 8 16 or 32 bits Reads to the LCSR and GCSR may be 8 16 or 32 bits Byte reads should be used to read the interrupt vector 4 This area does not return an acknowledge signal If the local bus timer is enabled the access times out and is terminated by a TEA signal 5 Size is approximate 6 Port commands to the 82596CA must be written as two 16 bit writes upper word first a...

Page 47: ...bus Accesses to the Local Bus The VMEchip2 includes a user programmable map decoder for the VMEbus to local bus interface The map decoder allows you to program the starting and ending address and the modifiers that the MVME162LX responds to VMEbus Short I O Memory Map The VMEchip2 includes a user programmable map decoder for the GCSR The GCSR map decoder allows you to program the starting address ...

Page 48: ...1 34 Board Level Hardware Description 1 ...

Page 49: ...tems are present Save the packing material for storing and reshipping of equipment Caution Avoid touching areas of integrated circuitry static discharge can damage circuits Hardware Preparation To select the desired configuration and ensure proper operation of the MVME162LX certain option modifications may be necessary before installation The MVME162LX provides software control for most of these o...

Page 50: ...abled J14 SRAM backup power source selection No jumper 1 3 2 4 3 5 4 6 1 3 4 6 3 5 2 4 Backup power disabled Primary VMEbus 5V STBY secondary VMEbus 5V STBY Primary onboard battery secondary onboard battery Primary VMEbus 5V STBY secondary onboard battery Primary onboard battery secondary VMEbus 5V STBY J16 Flash write protection No jumper 1 2 Flash write protection on writes disabled Flash write ...

Page 51: ...r function by moving the jumper to J1 pins 2 and 3 the MVME162LX determines whether it is the system controller by its position on the bus If the board is in the first slot from the left it configures itself as the system controller If the MVME162LX is not to be system controller under any circumstances remove the jumper from J1 When the board is functioning as system controller the SCON LED is tu...

Page 52: ... 20 J2 DS2 DS1 1 2 1 J1 49 50 24 25 27 26 2 1 J6 49 J8 J5 J7 4 2 3 J19 SCSI INTERFACE CSL FUSES FAIL RUN SCON ABORT RESET 99 100 1 2 J15 49 50 24 25 27 26 2 1 49 50 24 25 27 26 2 1 49 50 24 25 27 26 2 1 3 J9 8 1 15 9 J23 34 2 33 1 68 67 36 35 A B C D 2 8 1 7 2 8 1 7 2 8 1 7 2 8 1 7 J17 99 100 1 2 J22 J21 16 15 2 1 J20 16 2 1 1 J18 1 2 15 J16 1 2 J11 3 1 2 6 J14 1 5 J12 2 1 1 3 2 4 ETHERNET PORT BT...

Page 53: ...3 the IP bus clock speed is the same as that of the MC68040 bus clock that is 32MHz allowing the IP module to run with a 32MHz MPU Regardless of the IP bus clock setting all IP ports operate at the same speed Caution The IP32 CSR bit IP2 chip register at offset 1D bit 0 must be set to correspond to the jumper setting This is cleared 0 for 8MHz or set 1 for 32MHz If the jumper and the bit are not c...

Page 54: ...ader J14 Header J14 determines the source for onboard static RAM backup power on the MVME162LX The following backup power configurations are available for onboard SRAM through header J14 In the factory configuration the VMEbus 5V standby voltage serves as primary and secondary power source the onboard battery is disconnected Note For MVME162LXs without the optional VMEbus interface i e without the...

Page 55: ... a jumper installed on J16 the Flash memory can be written to via normal software routines When the jumper is removed the factory configuration Flash memory cannot be written to J14 Factory configuration 5 6 J14 Backup Power Disabled Primary Source Onboard Battery 1 2 5 6 1 2 J14 5 6 1 2 J14 5 6 1 2 J14 5 6 1 2 Secondary Source Onboard Battery Primary Source VMEbus 5V STBY Secondary Source VMEbus ...

Page 56: ...umper is removed from J18 the strobe line is available for a sideband type of messaging between IP modules The Strobe signal is not connected to any active devices on the board but it may be connected to a pull up resistor IP DMA Snoop Control Header J19 The jumpers on header J19 define the state of the snoop control bus when an IP DMA controller is local bus master Placing a jumper on J19 pins 3 ...

Page 57: ...ed separately The EPROM locations are standard JEDEC 32 pin DIP sockets The EPROM sockets accommodate three jumper selectable densities 256 Kbit x 8 512 Kbit x 8 the default configuration 1 Mbit x 8 and permit disabling of the Flash memory Header J20 provides eight jumper locations to configure the EPROM sockets Table 2 2 J19 Snoop Control Encoding Pins 1 2 Pins 3 4 Snoop Operation X 0 Snoop disab...

Page 58: ...21 pins 7 8 is a control bit in the MC2chip ASIC that determines whether reset code is fetched from Flash memory or from EPROMs J20 15 1 2 16 CONFIGURATION 4 1M x 8 EPROMs ONBOARD FLASH DISABLED J20 15 1 2 16 CONFIGURATION 3 1M x 8 EPROMs J20 15 1 2 16 CONFIGURATION 2 512K x 8 EPROMs J20 15 1 2 16 CONFIGURATION 1 256K x 8 EPROMs FACTORY DEFAULT ...

Page 59: ...ng 512K x 8 EPROMs GPI3 Address Range Device Accessed Removed 1 FF800000 FF87FFFF EPROM A XU1 FF880000 FF8FFFFF EPROM B XU2 FFA00000 FFBFFFFF Onboard Flash Installed 0 FF800000 FF9FFFFF Onboard Flash FFA00000 FFA7FFFF EPROM A XU1 FFA80000 FFAFFFFF EPROM B XU2 Table 2 5 EPROM Flash Mapping 1M x 8 EPROMs GPI3 Address Range Device Accessed Removed 1 FF800000 FF8FFFFF EPROM A XU1 FF900000 FF9FFFFF EPR...

Page 60: ...14 15 16 Note Pins 7 8 GPI3 are reserved to select either the Flash memory map jumper installed or the EPROM memory map jumper removed They are not user definable The address ranges for the various EPROM Flash configurations appear in the section on header J20 In most cases the MVME162LX is shipped from the factory with J21 set to all zeros jumpers on all pins except for GPI3 pins 7 8 On boards bu...

Page 61: ...ttom only it must be either the only mezzanine or the top mezzanine All ECC DRAM boards have two connector options Connectors top and bottom for stackability Connectors on the bottom only must be either the only mezzanine or the top mezzanine J21 15 GPI0 GPI1 GPI2 GPI6 GPI3 GPI4 GPI5 1 2 16 GPI7 EPROMs Selected factory configuration except on no VMEbus models REFER TO 162BUG MANUAL REFER TO 162BUG...

Page 62: ...sions have double wide front panels Installation Instructions This section covers Installation of IndustryPacks IPs on the MVME162LX Installation of the MVME162LX in a VME chassis System considerations relevant to the installation Before installing IndustryPacks ensure that EPROM devices are installed as needed and that all header jumpers are configured as desired Table 2 7 Memory Mezzanine Stacki...

Page 63: ..._ab into J5 J6 J7 and J8 2 Two additional 50 pin connectors J3 and J4 are provided behind the MVME162LX front panel for external cabling connections to the IP modules There is a one to one correspondence between the signals on the cabling connectors and the signals on the associated IP connectors i e J4 has the same IP_a signals as J5 J3 has the same IP_b signals as J7 Connect user supplied 50 pin...

Page 64: ...l for the equipment 3 Remove the filler panel from the card slot where you are going to install the MVME162LX If you intend to use the MVME162LX as system controller it must occupy the leftmost card slot slot 1 The system controller must be in slot 1 to correctly initiate the bus grant daisy chain and to ensure proper operation of the IACK daisy chain driver If you do not intend to use the MVME162...

Page 65: ... apply to such backplane designs 7 Connect the appropriate cable s to the MVME162LX panel connectors for the EIA 232 D serial ports SCSI port and LAN Ethernet port Note that some cables are not provided with the MVME162LX and must be made or purchased by the user Motorola recommends shielded cable for all peripheral connections to minimize radiation 8 Connect the peripheral s to the cable s 9 Inst...

Page 66: ...mer s Reference Guide The MVME162LX contains shared onboard DRAM whose base address is software selectable Both the onboard processor and offboard VMEbus devices see this local DRAM at base physical address 00000000 as programmed by the MVME162Bug firmware This may be changed via software to any other base address Refer to the MVME162LX Embedded Controller Programmer s Reference Guide for more inf...

Page 67: ...emote reset connector IndustryPack 5V and 12V The FUSES LED illuminates to indicate that all fuses are functioning correctly If a fuse opens you will have to remove power for several minutes to let the fuse reset to a closed or shorted condition The MVME162LX uses two Zilog Z85230 serial port controllers to implement the four serial communications interfaces Each interface supports CTS DCD RTS and...

Page 68: ...gure 2 2 DB 25 DTE to RJ 45 Adapter Figure 2 3 diagrams the pin assignments required in a cable to adapt a DB 25 DCE device to a RJ 45 connector Figure 2 3 DB 25 DCE to RJ 45 Adapter TXD RXD RTS CTS DTR DCD 1 2 3 4 5 6 7 8 DB 25 DTE DEVICE RJ 45 JACK 6 8 4 2 3 7 5 20 DSR SG TXD RXD RTS CTS DTR DCD 1 2 3 4 5 6 7 8 DB 25 DCE DEVICE RJ 45 JACK 8 4 2 3 7 5 20 SG ...

Page 69: ...n assignments required in a typical 8 conductor serial cable having RJ 45 connectors at both ends Note that all wires are crossed Figure 2 4 Typical RJ 45 Serial Cable RXD TXD CTS RTS DCD DTR 1 2 3 4 5 6 7 8 RJ 45 CONNECTOR RJ 45 CONNECTOR 8 7 5 4 6 2 1 SG 3 SG ...

Page 70: ...2 22 Hardware Preparation and Installation 2 ...

Page 71: ... Description of 162Bug The 162Bug package MVME162Bug is a powerful evaluation and debugging tool for systems built around the MVME162LX CISC based microcomputers Facilities are available for loading and executing user programs under complete operator control for system evaluation 162Bug includes commands for display and modification of memory breakpoint and tracing capabilities a powerful assemble...

Page 72: ... of the debugger commands You may switch between directories by using the Switch Directories SD command or you may examine the commands in your current directory by using the Help HE command Because 162Bug is command driven it performs its various operations in response to user commands entered at the keyboard When you enter a command 162Bug executes the command and the prompt reappears However if...

Page 73: ...des a pre calculated checksum contained in the memory devices is tested for an expected zero Thus users are cautioned against modification of the memory devices unless re checksum precautions are taken Installation and Startup Follow the steps below to operate 162Bug with the MVME162LX module 162Bug is factory installed in EPROM except in the no VMEbus case Caution Inserting or removing boards whi...

Page 74: ...local Static RAM for its work page i e variables stack vector tables etc Bit 1 GPI1 3 4 When set to 1 high instructs the debugger to use the default setup operation parameters in Flash or ROM versus the user setup operation parameters in Non Volatile RAM NVRAM This is the same as depressing the RESET and ABORT switches at the same time This feature can be used in the event the user setup is corrup...

Page 75: ...ry configuration puts a jumper between J18 pins 1 and 2 to connect the Strobe signal to the IP2 chip Verify that the strobe line should be connected in your application 5 The jumpers on header J19 enable disable the IP DMA snoop function on the MVME162LX The factory configuration has J19 fully jumpered to inhibit the snoop function Verify that snooping should be disabled in your IP DMA application...

Page 76: ...tors connect the appropriate cables and configure the port s as detailed in step 4 above After power up you can reconfigure this these port s by programming the MVME162LX Z85230 Serial Communications Controllers SCCs or by using the 162Bug PF command 9 EPROM Flash configuration header J20 should be set to configuration 2 with jumpers between J20 pins 5 and 6 8 and 10 and 9 and 11 This sets it up f...

Page 77: ...the debugger out of Flash memory rather than from PROM in subsequent sessions proceed as follows after the board is up and running 1 Install a jumper across J16 pins 1 2 to enable Flash writes 2 Copy the PROM contents to Flash memory with the PFLASH command as follows 162 Bug PFLASH FF800000 80000 FFA00000 3 Remove the jumper from J16 pins 1 2 to disable subsequent Flash writes 4 Install a jumper ...

Page 78: ...nted to within the volume ID of the media specified is loaded into RAM and control passed to it If however during this time you want to gain control without Autoboot you can press the BREAK key or the software ABORT or RESET switches Autoboot is controlled by parameters contained in the ENV command These parameters allow the selection of specific boot devices and files and allow programming of the...

Page 79: ...use of ROMboot might be resetting SYSFAIL on an unintelligent controller module The NORB command disables the function For a user s ROMboot module to gain control through the ROMboot linkage four requirements must be met Power must have just been applied but the ENV command can change this to also respond to any reset Your routine must be located within the MVME162LX Flash PROM memory map but the ...

Page 80: ...d device LUNs are valid the following message is displayed at the system console Network Boot in progress To abort hit BREAK Following this message there is a delay to let you abort the autoboot process if you wish Then the actual I O is begun the program pointed to within the volume ID of the media specified is loaded into RAM and control passed to it If however during this time you want to gain ...

Page 81: ... system initialization takes place as if the MVME162LX had just been powered up All static variables including disk device and controller parameters are restored to their default states The breakpoint table and offset registers are cleared The target registers are invalidated Input and output character queues are cleared Onboard devices timer serial ports etc are reset and the two serial ports are...

Page 82: ...the BREAK key on the terminal keyboard Break does not generate an interrupt The only time break is recognized is when characters are sent or received by the console port Break removes any breakpoints in your code and keeps the breakpoint table intact Break also takes a snapshot of the machine state if the function was entered using SYSCALL This machine state is then accessible to you for diagnosti...

Page 83: ...er definable parameter housed in NVRAM refer to the CNFG command description in Appendix A If the check fails a warning message is displayed The calculated clock speed is also checked against known clock speeds and tolerances Memory Requirements The program portion of 162Bug is approximately 512KB of code consisting of download debugger and diagnostic packages and contained entirely in Flash or PR...

Page 84: ...f contiguous read write memory to operate The ENV command controls where this block of memory is located Regardless of where the onboard RAM is located the first 64KB is used for 162Bug stack and static variable space and the rest is reserved as user space Whenever the MVME162LX is reset the target PC is initialized to the address corresponding to the beginning of the user space and the target sta...

Page 85: ...d as well as a list of the default configurations for each controller Blocks Versus Sectors The logical block defines the unit of information for disk devices A disk is viewed by 162Bug as a storage area divided into logical blocks By default the logical block size is set to 256 bytes for every block device in the system The block size can be changed on a per device basis with the IOT command The ...

Page 86: ...ds These following 162Bug commands are provided for disk I O Detailed instructions for their use are found in the Debugging Package for Motorola 68K CISC CPUs User s Manual When a command is issued to a particular controller LUN and device LUN these LUNs are remembered by 162Bug so that the next disk command defaults to use the same controller and device IOI Input Output Inquiry This command is us...

Page 87: ...O Bootstrap Operating System BO reads an operating system or control program from the specified device into memory and then transfers control to it BH Bootstrap and Halt BH reads an operating system or control program from a specified device into memory and then returns control to 162Bug It is used as a debugging tool Disk I O via 162Bug System Calls All operations that actually access the disk ar...

Page 88: ...roller specific packet which is then sent to the specified device Refer to the system call descriptions in the Debugging Package for Motorola 68K CISC CPUs User s Manual for details on the format and construction of these standardized user packets The packets which a controller module expects to be given vary from controller to controller The disk driver module for the particular hardware module b...

Page 89: ...n you invoke one of these commands the configuration area of the disk is read and the parameters corresponding to that device are rewritten according to the parameter information contained in the configuration area This is a temporary change If a cold start reset occurs then the default parameter information is written back into the tables Using the IOT You can use this command to reconfigure the ...

Page 90: ...tel 82596 LAN Coprocessor Management is in the scope of the reception of packets the transmission of packets receive buffer flushing and interface initialization This module ensures that the packaging and unpackaging of Ethernet packets is done correctly in the Boot PROM UDP IP Protocol Modules The Internet Protocol IP is designed for use in interconnected systems of packet switched computer commu...

Page 91: ... address the address of a server host and the name of a file to be loaded into memory and executed TFTP Protocol Module The Trivial File Transfer Protocol TFTP is a simple protocol to transfer files It is implemented on top of the Internet User Datagram Protocol UDP or Datagram so it may be used to move files between machines on different networks implementing UDP The only thing it can do is read ...

Page 92: ... issuing a remote GO command using the Multiprocessor Control Register MPCR The MPCR located at shared RAM location of 800 offset from the base address the debugger loads it at contains one of two longwords used to control communication between processors The MPCR contents are organized as follows The status codes stored in the MPCR are of two types Status returned from the monitor Status set by t...

Page 93: ...ons used for multi processor support 800 through 807 The MPCR contains 00 at powerup indicating that initialization is not yet complete As the initialization proceeds the execution path comes to the prompt routine Before sending the prompt this routine places an R in the MPCR to indicate that initialization is complete Then the prompt is sent If no terminal is connected to the port the MPCR is sti...

Page 94: ...2LX execution address in general purpose registers 0 and 1 GPCSR0 and GPCSR1 The remote processor then sets bit 8 SIG0 of the VMEchip2 LM SIG register This causes the MVME162LX to install breakpoints and begin execution The result is identical to the MPCR method with status code B described in the previous section The GCSR registers are accessed in the VMEbus short I O space Each general purpose r...

Page 95: ... instructions on how to invoke them Note that some diagnostics depend on restart defaults that are set up only in a particular restart mode The documentation for such diagnostics includes restart information Manufacturing Test Process During the manufacturing process for MVME162LXs the manufacturing test parameters and testing state flags are stored in NVRAM These strings are installed during the ...

Page 96: ...3 26 Debugger General Information 3 If either string is in the first location of NVRAM FFFC0000 the test process starts ...

Page 97: ...ntering Debugger Command Lines 162Bug is command driven and performs its various operations in response to user commands entered at the keyboard When the debugger prompt 162 Bug appears on the terminal screen then the debugger is ready to accept commands Terminal Input Output Control As the command line is entered it is stored in an internal buffer Execution begins only after the carriage return i...

Page 98: ...to the debugger depending on what the user program does For example if a breakpoint has been specified then control returns to the debugger when the breakpoint is encountered during execution of the user program Alternately the user program could return to the debugger by means of the TRAP 15 RETURN function X cancel line The cursor is backspaced to the beginning of the line H backspace The cursor...

Page 99: ...tax The metasymbols used are Syntactic Variables The following syntactic variables are encountered in the command descriptions which follow In addition other syntactic variables may be used and are defined in the particular command description in which they occur Expression as a Parameter An expression can be one or more numeric values separated by one of the arithmetic operators plus minus multip...

Page 100: ... quote mark The numeric value is interpreted as the concatenation of the ASCII values of the characters This value is right justified as any other numeric value would be Evaluation of an expression is always from left to right unless parentheses are used to group part of the expression There is no operator precedence Subexpressions within parentheses are evaluated first Nested parenthetical subexp...

Page 101: ...any commands use addr as a parameter The syntax accepted by 162Bug is similar to the one accepted by the MC68040 one line assembler All control addressing modes are allowed An address offset register mode is also provided Expression Result In Hex Notes FF0011 FF0011 45 99 DE 45 99 90 35 67 10 5C 10011110 1001 A7 88 4 880 shift left AA F0 A0 logical AND ...

Page 102: ... A1 Address register indirect with displacement two formats accepted d An Xn or d An Xn 120 A1 D2 120 A1 D2 Address register indirect with index and displacement two formats accepted bd An Xn od C A2 A3 100 Memory indirect preindexed bd An Xn od 12 A3 D2 10 Memory indirect postindexed For the memory indirect modes fields can be omitted For example three of many permutations are as follows An od A1...

Page 103: ...gram The offset registers solve this problem by taking into account this difference and forcing the display of addresses in a relative address offset format Offset registers have adjustable ranges and may even have overlapping ranges The range for each offset register is set by two addresses base and top Specifying the base and top addresses for an offset register sets its range In the event that ...

Page 104: ...rs the disassembled code addresses can be made to match the listing file addresses as follows 162 Bug OF R0 R0 00000000 00000000 1327C CR 162Bug MD 0 R0 DI CR 00000 R0 48E78080 MOVEM L D0 A0 A7 00004 R0 4280 CLR L D0 00006 R0 1018 MOVE B A0 D0 00008 R0 5340 SUBQ W 1 D0 0000A R0 12D8 MOVE B A0 A1 0000C R0 51C8FFFC DBF D0 A R0 00010 R0 4CDF0101 MOVEM L A7 D0 A0 00014 R0 4E75 RTS 162 Bug 8 0 00000008...

Page 105: ...on the MVME162LX J17 front panel connector Sometimes known as the host port this is the default for downloading uploading concurrent mode and transparent modes 3 MVME162 EIA 232 D Terminal Ports 2 or 02 and 3 or 03 Port 3 and Port 4 on the MVME162LX J17 front panel connector Additional serial ports available Note These logical port numbers 0 1 2 and 3 are shown in the pinouts of the MVME162LX modu...

Page 106: ...mat described in the Debugging Package for Motorola 68K CISC CPUs User s Manual and may have been assembled or compiled on the host system Alternately the program may have been previously created using the 162Bug MM command as outlined above and stored to the host using the Dump DU command A communication link must exist between the host system and port 2 on the MVME162LX Hardware configuration de...

Page 107: ...n explains how to avoid contaminating the operating environment of the debugger Topics covered include 162Bug Vector Table and workspace Hardware functions Exception vectors used by 162Bug 162Bug uses certain of the MVME162LX onboard resources and may also use offboard system memory to contain temporary variables exception vectors etc If you disturb resources upon which 162Bug depends then the deb...

Page 108: ...example your program inadvertently wrote over the static variable area containing the serial communication parameters these parameters would be lost resulting in a loss of communication with the system console terminal If your program corrupts the system stack then an incorrect value may be loaded into the processor Program Counter PC causing a system crash 162Bug reserves For 1024 byte area A use...

Page 109: ...cilities breakpoints trace mode etc to operate When the debugger handles one of the exceptions listed in Table 4 2 the target stack pointer is left pointing past the bottom of the exception stack frame created that is it reflects the system stack Table 4 2 Exception Vectors Used by 162Bug Vector Offset Exception 162Bug Facility 10 Illegal instruction Breakpoints used by GO GN GT 24 Trace Trace ope...

Page 110: ...A1 00000000 A2 00000000 A3 00000000 A4 00000000 A5 00000000 A6 00000000 A7 0000FFFC IPLR 00000007 IML R 00000000 MMIE N 00000003 VIEN C0000000 VIST 00000000 PIEN 00002000 PIST 00000000 00010000 203C0000 0001MOVE L 1 D0 172 Bug t PC 00010006 SR 2700 TR OFF_S _7_ VBR 00000000 SSP 0000FFFC USP 00010000 SFC 1 UD DFC 1 UD CACR 00000000 D _B _I PCR 04310402 D0 00000001 D1 00000000 D2 00000000 D3 0000000...

Page 111: ...able area is the base address 00 of the debugger memory This address is loaded into the target state VBR at power up and cold start reset and can be observed by using the RD command to display the target state registers immediately after power up The 162Bug initializes the target vector table with the debugger vectors listed in Table 4 2 on page 4 13 and fills the other vector locations with the a...

Page 112: ... in the event that your program is stopped by an unexpected exception The generalized exception handler gives a formatted display of the target registers and identifies the type of the exception The following is an example of a routine which builds a separate vector table and then moves the VBR to point at it BUILDX Build exception vector table BUILDX MOVEC L VBR A0 Get copy of VBR LEA 10000 A1 Ne...

Page 113: ...ctor location which is the address of the 162Bug exception handler Your program must make sure that there is an exception stack frame in the stack and that it is exactly the same as the processor would have created for the particular exception before jumping to the address of the exception handler The following is an example of an exception handler which can pass an exception along to the debugger...

Page 114: ...cision Real Format or Scientific Notation Valid data types that can be used when modifying a floating point data register or a floating point memory location When entering data in single or double precision you must observe the following rules 1 The sign field is the first field and is a binary field 2 The exponent field is the second field and is a hexadecimal field 3 The mantissa field is the la...

Page 115: ... Single Precision Real This format would appear in memory as A single precision number takes 4 bytes in memory Double Precision Real This format would appear in memory as A double precision number takes 8 bytes in memory Note The single and double precision formats have an implied integer bit always 1 1 bit sign field 1 binary digit 8 bit biased exponent field 2 hex digits Bias 7F 23 bit fraction ...

Page 116: ...al Exponent field that consists of An optional underscore The Exponent field identifier letter E An optional Exponent sign From 1 to 3 decimal digits For more information about the MC68040 floating point unit refer to the MC68040 Microprocessor User s Manual The 162Bug Debugger Command Set The 162Bug debugger commands are summarized in Table 4 3 The command syntax is shown using the symbols explai...

Page 117: ...ve BM range addr B W L BO Bootstrap Operating System BO controller LUN device LUN string BR Breakpoint Insert BR addr count NOBR Breakpoint Delete NOBR addr BS Block of Memory Search BS range text B W L or BS range data mask B W L N V BV Block of Memory Verify BV range data increment B W L CM Concurrent Mode CM port ID string baud phone number A H NOCM No Concurrent Mode NOCM CNFG Configure Board ...

Page 118: ...cess IOP IOT I O TEACH for Configuring Disk Controller IOT A F H T IRQM Interrupt Request Mask IRQM mask LO Load S records from Host LO port addr X C T text MA Macro Define Display MA name L NOMA Macro Delete NOMA name MAE Macro Edit MAE name line string MAL Enable Macro Expansion Listing MAL NOMAL Disable Macro Expansion Listing NOMAL MAW Save Macros MAW controller LUN device LUN del block MAR Lo...

Page 119: ...roller LUN device LUN client IP Address server IP Address string NIOC Network I O Control NIOC NIOP Network I O Physical NIOP NIOT Network I O Teach NIOT H A NPING Network Ping NPING controller LUN device LUN source IP destination IP n packets OF Offset Registers Display Modify OF Rn A PA Printer Attach PA port NOPA Printer Detach NOPA port PF Port Format PF port NOPF Port Detach NOPF port PFLASH ...

Page 120: ...ddyyhhmm n C SYM Symbol Table Attach SYM addr NOSYM Symbol Table Detach NOSYM SYMS Symbol Table Display Search SYMS symbol name S T Trace T count TA Terminal Attach TA port TC Trace on Change of Control Flow TC count TIME Display Time and Date TIME C L O TM Transparent Mode TM port ESCAPE TT Trace to Temporary Breakpoint TT addr VE Verify S Records Against Memory VE port addr X C text VER Display ...

Page 121: ... the board information block and lists the size and logical offset of each element The CNFG command does not describe the elements and their use The board information block contents are checksummed for validation purposes This checksum is the last element of the block Although the factory fills all fields except the IndustryPack fields only these fields MUST contain correct information MPU clock s...

Page 122: ...C Board Identifier IndustryPack C PWA Serial Number IndustryPack C Artwork PWA Identifier IndustryPack D Board Identifier IndustryPack D PWA Serial Number IndustryPack D Artwork PWA Identifier 162 Bug Note that the parameters that are quoted are left justified character ASCII strings padded with space characters and the quotes are displayed to indicate the size of the string Parameters that are no...

Page 123: ...d up RAM BBRAM also known as non volatile RAM NVRAM The operational parameters are saved in NVRAM and used whenever power is lost Whenever the Bug uses a parameter from NVRAM the NVRAM contents are first tested by checksum to insure the integrity of the NVRAM contents In the instance of BBRAM checksum failure certain default values are assumed as stated below The bug operational parameters which a...

Page 124: ...cessor Control Register MPCR in shared RAM methods to pass and start execution of cross loaded programs Probe System for Supported I O Controllers Y N Y Accesses will be made to the appropriate system busses e g VMEbus local MPU bus to determine presence of supported controllers Negate VMEbus SYSFAIL Always Y N N Negate VMEbus SYSFAIL after successful completion or entrance into the bug command mo...

Page 125: ... is passed on to the code being booted Maximum length is 16 characters Default is the null string ROM Boot Enable Y N N ROMboot function is disabled ROM Boot at power up only Y N Y ROMboot is attempted at power up only ROM Boot Enable search of VMEbus Y N N VMEbus address space will not be accessed by ROMboot ROM Boot Abort Delay 00 The time in seconds that the ROMboot sequence will delay before s...

Page 126: ...ping the boot by use of the Break key The time value is from 0 through 255 seconds Network Autoboot Configuration Parameters Pointer NVRAM 00000000 The address where the network interface configuration parameters are to be saved retained in NVRAM these parameters are the necessary parameters to perform an unattended network boot Memory Search Starting Address 00000000 Where the Bug begins to searc...

Page 127: ...ry Search Ending Address is the calculated size of local memory Memory Search Increment Size 00010000 A multi CPU feature used to offset the location of the Bug work page This must be a multiple of the debugger work page modulo 10000 64KB Typically Memory Search Increment Size is the product of CPU number and size of the Bug work page Example first CPU 0 0 x 10000 second CPU 10000 1 x 10000 etc Me...

Page 128: ...veral Bugs will reside in the memory of the primary first MVME162LX the non primary CPUs will wait for the data at the Memory Search Delay Address to be set to 00 01 or 02 refer to the Memory Requirements section in Chapter 3 for the definition of these values before attempting to locate their work page in the memory of the primary CPU Memory Size Enable Y N Y Memory will be sized for Self Test di...

Page 129: ...ory Parity and or ECC type memory It must be a multiple of the Dynamic Memory board size starting with 0 Default is 0 Size of Parity Memory 00100000 This is the size of the Parity type dynamic RAM mezzanine if any The default is the calculated size of the Dynamic memory mezzanine board Size of ECC Memory Board 0 00000000 This is the size of the first ECC type memory mezzanine The default is the ca...

Page 130: ...address of the local resource that is accessible by the VMEbus Default is the end of calculated memory Slave Address Translation Address 1 00000000 Register that allows the VMEbus address and the local address to be different The value in this register is the base address of local resource that is associated with the starting and ending address selection from the previous questions Default is 0 Sl...

Page 131: ...accessible from the local bus Default is the end of calculated local memory unless memory is less than 16MB then this register will always be set to 01000000 Master Ending Address 1 EFFFFFFF Ending address of the VMEbus resource that is accessible from the local bus Default is the end of calculated memory Master Control 1 0D Defines the access characteristics for the address space defined with thi...

Page 132: ...ulated as one more than the calculated size of memory If not enabled the default is 00000000 Master Ending Address 3 00000000 Ending address of the VMEbus resource that is accessible from the local bus If enabled the default is 00FFFFFF otherwise 00000000 Master Control 3 00 Defines the access characteristics for the address space defined with this master address decoder If enabled the default is ...

Page 133: ...ss Decoder Short I O VMEbus A16 Control 01 Defines the access characteristics for the address space defined with the Short I O address decoder Default is 01 F Page VMEbus A24 Enable Y N Y Yes enable the F Page Address Decoder F Page VMEbus A24 Control 02 Defines the access characteristics for the address space defined with the F Page address decoder Default is 02 ROM Access Time Code 04 Defines th...

Page 134: ...applicable to IP_c and IP_d are not used in the 700 800 series MVME162LX IP A Base Address 00000000 IP B Base Address 00000000 IP C Base Address 00000000 IP D Base Address 00000000 VMEC2 GCSR Group Base Address D2 Specifies the group address FFFFXX00 in Short I O for this board Default D2 VMEC2 GCSR Board Base Address 00 Specifies the base address FFFFD2XX in Short I O for this board Default 00 VM...

Page 135: ... 00000000 Define the memory size requirements for the IP modules IP D C B A General Control 00000000 Define the general control requirements for the IP modules Bits IP Register Address 31 24 D FFFBC00F 23 16 C FFFBC00E 15 08 B FFFBC00D 07 00 A FFFBC00C Bits IP Register Address 31 24 D FFFBC01B 23 16 C FFFBC01A 15 08 B FFFBC019 07 00 A FFFBC018 ...

Page 136: ... warning message will appear if you have specified environment parameters that will cause an overlap condition The important information about each configurable element in the memory map is displayed showing where any overlap conditions exist This will allow you to quickly identify and correct an undesirable configuration before it is saved Bits IP Register Address 31 24 D FFFBC016 23 16 C FFFBC01...

Page 137: ...0000000 00FFFFFF Yes Yes Master VMEbus Master 3 00000000 00000000 No No Master VMEbus Master 4 F0000000 FF7FFFFF Yes Yes Master VMEbus F Pages A24 A32 FFFF0000 FFFFFFFF Yes Yes Master VMEbus Short I O A16 FF800000 FFBFFFFF Yes Yes Master Flash PROM FFF00000 FFFEFFFF Yes Yes Master Local I O 00000000 00000000 No No Master Industry Pack A 00000000 00000000 No No Master Industry Pack B 00000000 00000...

Page 138: ...A 18 Configure and Environment Commands A ...

Page 139: ... that if another controller of the same type is used the second one must have its address changed by its onboard jumpers and or switches so that it matches the Second Address value and can be called up by the Second CLUN value Controller Type First CLUN First Address Second CLUN Second Address CISC Embedded Controller 00 MVME328 SCSI Controller 1 06 FFFF9000 07 FFFF9800 MVME328 SCSI Controller 2 1...

Page 140: ...ices are the only ones tested by Motorola Computer Group CISC Embedded Controllers 7 Devices Controller LUN Address Device LUN Device Type 0 XXXXXXXX 00 10 20 30 40 50 60 SCSI Common Command Set CCS which may be any of these Fixed direct access Removable flexible direct access TEAC style CD ROM Sequential access ...

Page 141: ... 00 08 10 18 20 28 30 SCSI Common Command Set CCS which may be any of these Removable flexible direct access TEAC style CD ROM Sequential access 7 FFFF9800 16 FFFF4800 40 48 50 58 60 68 70 Same as above but these are only available if the daughter card for the second SCSI channel is present 17 FFFF5800 18 FFFF7000 19 FFFF7800 ...

Page 142: ...2 2 2 Block Size 0 128 1 256 2 512 3 1024 4 2048 5 4096 1 1 1 1 1 1 1 Sectors Track 10 8 9 9 F 12 24 Number of Heads 2 2 2 2 2 2 2 Number of Cylinders 50 28 28 50 50 50 50 Precomp Cylinder 50 28 28 50 50 50 50 Reduced Write Current Cylinder 50 28 28 50 50 50 50 Step Rate Code 0 0 0 0 0 0 0 Single Double DATA Density D D D D D D D Single Double TRACK Density D D D D D D D Single Equal_in_all Track ...

Page 143: ...imal 653312 327680 368460 737280 1228800 1474560 2949120 Media Size Density 5 25 DD 5 25 DD 5 25 DD 3 5 DD 5 25 HD 3 5 HD 3 5 ED Notes 1 All numerical parameters are in hexadecimal format unless otherwise noted 2 The DSDD5 type floppy is the default setting for the debugger IOT Parameter Floppy Types and Formats DSDD5 PCXT8 PCXT9 PCXT9_3 PCAT PS2 SHD ...

Page 144: ...B 6 Disk Tape Controller Data B ...

Page 145: ...r commands NBH NBO NIOP NIOC NIOT NPING and NAB and also with the debugger system calls NETRD NETWR NETFOPN NETFRD NETCFIG and NETCTRL Controller Type CLUN DLUN Address Interface Type MVME162 00 00 FFF46000 Ethernet MVME376 1 02 00 FFFF1200 Ethernet MVME376 2 03 00 FFFF1400 Ethernet MVME376 3 04 00 FFFF1600 Ethernet MVME376 4 05 00 FFFF5400 Ethernet MVME376 5 06 00 FFFF5600 Ethernet MVME376 6 07 0...

Page 146: ...C 2 Network Controller Data C ...

Page 147: ...If the FUSES LED is not lit the board may not be getting correct power 1 Make sure the system is plugged in 2 Check that the board is securely installed in its backplane or chassis 3 Check that all necessary cables are connected to the board per this manual 4 Check for compliance with System Considerations per this manual 5 Review the Installation and Startup procedures per this manual They includ...

Page 148: ...ory is installed per this manual 3 Reconnect power 4 Restart the system by double button reset press the RESET and ABORT switches at the same time release RESET first wait seven seconds then release ABORT 5 If the debug prompt appears go to step IV or step V as indicated If the debug prompt does not appear go to step VI B The board may need to be reset IV Debug prompt 162 Bug appears at powerup bu...

Page 149: ... may need to use the cnfg command see your board Debugger Manual to change clock speed and or Ethernet Address and then later return to env CR and step 3 7 Run the selftests by typing in st CR The tests take as much as 10 minutes depending on RAM size They are complete when the prompt returns The onboard selftest is a valuable tool in isolating defects 8 The system may indicate that it has passed ...

Page 150: ...ired VI The board has failed one or more of the tests listed above and cannot be corrected using the steps given A There may be some fault in the board hardware or the on board debugging and diagnostic firmware 1 Document the problem and return the board for service 2 Phone 1 800 222 5640 TROUBLESHOOTING PROCEDURE COMPLETE Table D 1 Troubleshooting MVME162LX Boards Continued Condition Possible Pro...

Page 151: ...program with 4 10 assertion definition of 1 12 autoboot function 3 7 autojumpering function 2 17 B backplane jumpers 2 17 Backus Naur syntax debugger commands and 4 3 base address DRAM 2 18 base and top addresses 4 7 base identifier numeric values and 4 4 battery 1 18 battery backed up RAM BBRAM and clock 1 20 A 3 BBRAM battery backed up RAM and clock 1 20 BG Bus Grant signal 2 17 BH Bootstrap and...

Page 152: ...g 3 16 diagnostic facilities 3 25 direct access devices B 2 B 3 directories switching 3 25 disk I O error codes 3 19 support 3 15 via 162Bug commands 3 16 via 162Bug system calls 3 17 disk tape controller data B 1 DLUN device LUN B 2 C 1 documentation non Motorola single publications 1 5 other applicable Motorola publications 1 4 double precision real floating point format 4 19 double button reset...

Page 153: ...rements A 15 defining interrupt control requirements A 16 defining memory size requirements A 15 input output control terminal 4 1 installation considerations 2 18 IP IndustryPack modules 2 15 MVME162LX 2 16 2 18 installation and startup 3 3 instructions floating point 4 18 Intel 82596 LAN coprocessor 3 20 interface Ethernet 1 22 IndustryPack IP 1 22 SCSI 1 23 serial 1 21 serial communications 2 1...

Page 154: ...essor support 3 22 MVME162Bug 162Bug 1 16 2 3 3 1 MVME162LX block diagram 1 14 features 1 6 installation 2 16 specifications 1 8 MVME328 SCSI controller B 1 B 2 B 3 MVME374 376 LAN controllers C 1 N negation definition of 1 12 network boot control module 3 21 boot function 3 10 controller modules supported C 1 I O error codes 3 22 I O support 3 19 non volatile RAM NVRAM A 3 normal address range 1 ...

Page 155: ...AM Static RAM battery 1 18 options 1 17 S record files downloading 4 10 S record format 4 10 stacking mezzanine boards 2 13 startup MVME162LX 3 3 status bit definition of 1 12 string literals numeric values and 4 4 switches 1 13 switching directories 3 25 syntactic variables command lines and 4 3 system calls 162Bug 3 17 system console 3 5 system controller function 3 5 System Fail SYSFAIL signal ...

Page 156: ...Index IN 6 I N D E X W watchdog timer 1 24 Z Z85230 serial communications controllers SCCs 3 6 ...

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