B-5
∑
ANALOG
MUX
(EQUIVALENT)
START
SGL/DIF ODD/SIGN SELECT1 SELECT0
C
D
R
R
R
R
R
MUX
ADDRESS
5 BIT SHIFT REGISTER
VCC
B7
B6
B5
B4
B3
B2
B1
B0
8-BIT
SHIFT
REGISTER
SAR
LOGIC
AND
LATCH
EOC
COMP
EOC
CS
R
R
C
COMP
LSB FIRST
ONE
SHOT
PARALLEL
XFR TO
SHIFT REG
MSB FIRST
C
C
F1
C
L
Q
R
CS
L2
C
L
Q
R
L1
C
L
Q
R
CS
TD
TIME
DELAY
CS
CS
COMP
LADDER
AND
DECODER
TO INTERNAL
CIRCUITRY
7V ZENER
7V ZENER
INPUT
Vcc
R
TO
INTERNAL
CIRCUITS
13
16
17
18
INPUT PROTECTION - ALL LOGIC INPUTS
START CONV AND ENABLE
TSL OUTPUT BUFFER
17
18
16
1
2
3
4
5
6
7
8
9
12
20
19
10
11
14
15
13
SARS*
DO
D1
CLK
CH0*
CH1*
CH2*
CH3*
CH4*
CH5*
CH6*
CH7*
COM*
D GND*
A GND
+
V *
V
REF
V
CC
*Some of these functions/plns are not avallable with other options.
CS
SE*
START
IC406 ADC0838CCWM
OTP
ROM
with PLL
Divider
Values
PLL
Clock
Synthesis
and Control
Circuitry
Crystal
Oscillator
Output
Buffer
Divide
Logic and
Output
Buffer
Crystal
or clock
input
X1/CLK
X2
REF
CLK
1
8
2
3
7
5
4
VDD
GND
PDTS (both outputs and PLL)
IC408 ICS301M-62(XD200U)
ICS301M-66(SD200U)
IC409 NC7SZ02P5X
A
B
GND
V
CC
Y
1
2
3
5
4
Inputs
B
Y
A
Outputs
L
L
H
H
L
L
H
L
L
H
H
L
Y=A+B
H = HIGH Logic Level
L = LOW Logic Level
FUNCTION TABLE
Summary of Contents for SD200U
Page 108: ......
