RTE-V821-PC
USER’ S MANUAL
18
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PORT0
LED-P07
LED-P06
-
-
-
Reserved field 0
Output
PORT1
SW2[8..1]
Input
PORT2
PD[2..1]
TOVERF-
DSR-
DTR-
NMIMASK
TOVERCLR-
Reserved
field 1
Input
Output
PIO Bit Assignment
Each port bit is described below.
Reserved field 0
:
All the three bits in this field are reserved for the system. Once
they are initialized to 0, do not change them.
LED-P07 and LED-P06 :
These bits are used to turn on or off the LEDs on the board. When
a bit is reset to 0, the corresponding LED is turned off. When it is
set to 1, the LED is turned on.
SW2-[8..1]
:
The states of SW2 mounted on the board can be read-accessed.
SW2[1] corresponds to contact 1 of SW2, and SW2[8] corresponds
to contact 8 of SW2, and so on. When a switch is ON, the
corresponding bit is read as 0. When it is OFF, the corresponding
bit is read as 1.
Reserved field 1
:
The bit in this field is reserved for the system. Once the bit is
initialized to 1, do not change it.
TOVERCLR-
:
This is a control bit used to clear TOVERF- in bit 5 of port 2. It
should be initialized to 1 and usually kept to be 1. When TOVERF-
is to be cleared, the bit should be rest to 0, then set back to 1.
NMIMASK
:
This bit is used to mask an NMI signal input to the CPU. When the
bit is 1, the NMI signal is masked at a gate. The bit should be
initialized to 1. When an NMI becomes acceptable, the bit should
be reset to 0.
DTR-
:
This bit controls the DTR signal output from the JSIO connector.
The inverted state of this bit is converted to the RS-232C level and
output to the JSIO connector.
DSR-
:
This bit indicates the state of the DSR signal input from the JSIO
connector. The state of this bit represents the inverted state of the
DSR signal at the JSIO connector.
TOVERF-
:
This bit becomes 0, when 30 or more bus cycles occur to result in a
time-out. The flag is cleared (to 1), using bit 1 (TOVERCLR-) of
port 2.
PD[2..1]
:
PD[2..1] of a DRAM (72-pin SIMM) chip mounted on the board can
be read-accessed. The states of these bits indicate the size of the
DRAM area. The following table lists the relationships between
PD[2..1] and the DRAM capacity.
PD[2]
PD[1]
DRAM capacity
0
0
4 Mbytes
0
1
Reserved
1
0
16 Mbytes
1
1
8 Mbytes
PD[2..1] and DRAM Capacity
