RTE-V821-PC
USER’ S MANUAL
13
5. HARDWARE REFERENCES
This chapter describes the hardware of the RTE-V821-PC.
5.1. MEMORY MAP
The memory assignment of the board is shown below.
Image of
0000-0000 to
00FF-FFFF
Image 4000-
0000 to
40FF-FFFF
Image of
8000-0000 to
80FF-FFFF
Image of FF00-
0000 to FFFF-
FFFF
0 0 0 0 - 0 0 0 0
40FF-FFFF
8 0 0 0 - 0 0 0 0
4 0 0 0 - 0 0 0 0
7FFF-FFFF
3FFF-FFFF
00FF-FFFF
CS0 space
Reserved
8 0 0 0 - 0 0 0 0
8 0 1 0 - 0 0 0 0
8 0 2 0 - 0 0 0 0
800F-FFFF
801F-FFFF
80FF-FFFF
80FF-FFFF
C 0 0 0 - 0 0 0 0
BFFF-FFFF
F F 0 0 - 0 0 0 0
FF01-FFFF
F F 0 2 - 0 0 0 0
FF0F-FFFF
F F 1 0 - 0 0 0 0
FFAF-FFFF
FFBF-FFFF
FFB0-1000
FFB0-0FFF
FFB0-0000
FFC0-0000
FFEF-FFFF
F F F 0 - 0 0 0 0
FFFD-FFFF
FFFE-0000
F F 0 0 - 0 0 0 0
FFFF-FFFF
FFFF-FFFF
Image of
FF00-0000 to
FF01-FFFF
Image of
FFB0-0000 to
FFB0-0FFF
Image of FFFE-
0000 to FFFF-
FFFF
Not used
Not used
Not used
CS1 space
CS2 space
CS3 space
DRAM
Reserved
SRAM
EXT-BUS
SYSTEM-I/O
ROM
See the figure at
the right
See the figure at
the right
Memory Map
DRAM space (0000-0000H to 00FF-FFFFH)
This space is in a 72-pin SIMM chip mounted on the RTE-V821-PC board. A 4-Mbyte SIMM
chip is used in a standard configuration. It can be replaced with an 8- Mbyte or 16-Mbyte
SIMM chip for memory expansion. When the CPU clock frequency is 25 MHz, and an SIMM
chip having an access time of 70 ns or less is mounted, access is possible with three wait
states. DRAM control is performed using the DRAM controller of the V821, so it is necessary
to set internal I/O registers. See Section 5.2.3 for how to initialize.
Reserved spaces (4000-0000H to 7FFF-FFFFH, 8000-0000H to 800F-FFFFH)
These spaces are reserved for future use. Do not try to access them.
