RTE-V821-PC
USER’ S MANUAL
17
6. SYSTEM-I/O
SYSTEM-I/O is an I/O device mapped in a memory space. The I/O devices include the
UART/TIMER, PIO, and ISA bus interface. (No description about the ISA bus interface is
included.)
6.1. UART/TIMER (SCC2691)
The SCC2691 UART receiver/transmitter LSI chip produced by PHILIPS Signetics is used as the
UART/TIMER. Because the SCC2691 has a 3-character buffer in the receiver section, it is
possible to minimize chances of an overrun error occurring during reception. Moreover, a
3.6864 MHz oscillator is connected across the X1 and X2 pins. It, in conjunction with a 16-bit
counter in the SCC2691, enables measurement of about 271 ns to 17.8 ms.
Each register in the SCC2691 is assigned as listed below. Refer to the applicable SCC2691
manual for the function of each register.
Address
Read access
Write access
FFB0-0400h
MR1,MR2
MR1,MR2
FFB0-0402h
SR
CSR
FFB0-0404h
Reserved
CR
FFB0-0406h
RHR
THR
FFB0-0408h
Reserved
ACR
FFB0-040Ah
ISR
IMR
FFB0-040Ch
CTU
CTUR
FFB0-040Eh
(CTL)
CTLR
SCC2691 Register Map
The general-purpose output pin (MPO) and input pin (MPI) are used as RTS (RS) and CTS (CS),
respectively. DTR (DR) and DSR (ER) are controlled by the PIO. See Section 6.1.2 for
details.
The SCC2691 is reset at a system reset (see Section 8.1).
6.2. PIO (
µ
PD71055)
The uPD71055 produced by NEC is installed as a PIO. The uPD71055 is compatible with the
i8255 produced by Intel. It has three parallel ports. These ports are used for various types of
control. Each register of the PIO is assigned as listed below.
Address
Read access
Write access
FFB0-0800h
PORT0
PORT0
FFB0-0802h
PORT1
PORT1
FFB0-0804h
PORT2
PORT2
FFB0-0806h
---------
COMMAND REG
PIO Register Map
The PIO ports are reset at a system reset. When reset, all these ports are set as input, so the
signal state of each port bit used for output is set to a high level, using a pull-up resistor. The
following table lists the way each port bit is used.
