Technical Description
miriac MPX-LX2160A User Manual
V1.4
30/73
© MicroSys Electronics GmbH 2020
4.7
Reset Structure
The module’s r
eset chains are handled by the integrated CPLD. It also handles
some aspects of the boot source selection.
The following pins are used to control the module
’
s reset chain:
Module Connector
Description
Pin
Signal
I/O
I/O
Range
Signal
conditioning
Function
ST1: C4
PORESET#
IN
1.8V
CPU 4k7 PU
CPU power on reset,
low active
ST1: C5
HRESET#
IN /
OUT
1.8V
CPU 4k7 PU
Bidirectional hard reset,
low active
ST1:
C10
RESET_REQ#
OUT
1.8V
CPU 4k7 PU
Reset request to the CPU
driven by the CPLD,
low active
ST1:
A16
TRST_B
IN
1.8V
CPLD
JTAG reset, low active
ST1:
A10
RESIN#
IN
1.8V
CPLD (PU)
Reset input, used to trigger
a module reset, low active
ST1: A9
RESET_OUT#
OUT
1.8V
CPLD
Reset output, used to reset
peripheral devices on the
carrier, low active
ST1:
D41
RST_PHY#
OUT
1.8V
CPLD
Reset for Ethernet PHYs,
low active
ST2:
D21
RST_XSPI#
OUT
1.8V
CPLD
Reset for XSPI flashes,
low active
ST2:
H21
RST_OUT1_B
OUT
1.8V
CPLD
t.b.d, low active reset
ST2:
G21
RST_OUT2_D
ELAY_B
OUT
1.8V
CPLD
t.b.d, low active reset
ST2: F9
RST_OUT3_B
OUT
1.8V
CPLD
t.b.d, low active reset
ST2:
A15
RESET-ME#
IN
3.3V
STBY
ME 4k7 PU
Reset input to Management
Engine. Used for production
and debugging purposes
ST1:
C16
POR-RESET#
IN
3.3V
STBY
SEQUENCE
R, 10 PU
Reset input to Power
Sequencer.
Used for production and
debugging purposes
Table 4-5 Reset pins: pin assignments
PORESET# and HRESET# are directly connected to the SoC. Any circuitry on the
Carrier must ensure correct rise times and timing.
It is recommended not to use these signals. Use RESIN# and RESET_OUT# instead.
RESET_REQ# is an input to the SoC. It is connected to the module connector for
monitoring purposes only.
