VSC8257/VSC8258 Evaluation Board
ENT-AN1280 VPPD-04670 ENT-AN1280 User Guide Revision 1.3
12
Figure 13 • GUI Clocking Page
In this page, there are actually two main categories: the source for the output clocks and the source for
the lane sync feature.
For the output clocks, CKOUTn, the user can first enable that output and then select if the output clock
frequency should be divided by 1 or by 2. When it is divided by 2, the result is a 161 MHz clock output
derived from the selected source. When it is divided by 1, then the frequency will be 322 MHz. The
selection of the clock source include the host/line side CMU divided down clock or the host/line-side
recovered clock from data.
For the lane sync feature, the user can select the Tx clock of each channel (line or host) to be lane
synced (locked) to the local reference clock or the Rx clock of the same channel or the Rx clock from
other channels.
Note: When cross-connect is enabled, the Tx clocks of all host channels must be lane synced to the local
reference clock.
5.12
Command Line Interface
Clicking on
>
from the toolbar opens the command line interface (CLI) window. From
Board Vitesse CLI
here, users can load initialization files or other scripts. When the
button is clicked, another
Load Macro
window will appear allowing the user to select the script.
The following example describes WS_P03_81_ae_00_00_00_02_00 where WS is SPI command:
P03 is the port of the F340 processor used for the SPI
Bit 55 = 1 is write and = 0 is read
Bit 54:53 is the port/channel number: it is port 0
Bit 52:48 is device number: it is 0x1
Bit 47:32 is the register address: it is 0xAE00
Bit 31:0 is the value for the register: it is 0x000000200
The following images show the command line interface.
