VSC8257/VSC8258 Evaluation Board
ENT-AN1280 VPPD-04670 ENT-AN1280 User Guide Revision 1.3
9
Table 1 • Generator Configuration (GEN_CFG), Address: 4xE900
Bit
Name
Access
Description
Default
14:12
LENOFS
R/W
Decrease pktlen by lenofs
0x3
11:4
SRATE
R/W
Number of standard frames between PTP frames
0x00
2
IDLES
R/W
Generate all idles
0: Generate frames
1: Generate idles only
0x0
1
PTP_ENABLE
R/W
Generate PTP frames
0: Generate standard frames
1: Generate PTP frames
0x0
0
ENABLE
R/W
Enable packet generator
0: Generator is disabled
1: Generator is enabled
Pattern generator data cannot
Note:
simultaneously be inserted in the egress and
ingress data paths. Insertion of pattern
generator data into the paths is controlled by
4xEA20.7 and 4xEA20.8.
There are additional restrictions in using this bit
Note:
for 1G mode. Please consult the factory.
0x0
5.6
SFP+
The information of the SFP+ module registers could be read through the GPIOs of the VSC8258 that are
configured as I2C master to interface with the I2C registers of the SFP+, as shown.
Figure 8 • GUI SFP+ Page
5.7
Register List
The following image shows the register list page.
