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Revision History

UG0747 User Guide Revision 1.0

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Revision History

The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.

1.1

Revision 1.0

Revision 1.0 is the first publication of this document.

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Summary of Contents for UG0747

Page 1: ...UG0747 User Guide PolarFire FPGA Evaluation Kit ...

Page 2: ...e suitability of any products and to test and verify the same The information provided by Microsemi hereunder is provided as is where is and with all faults and the entire risk associated with such information is entirely with the Buyer Microsemi does not grant explicitly or implicitly to any party any patent rights licenses or any other IP rights whether with regard to such information itself or ...

Page 3: ...urces 10 4 Board Components and Operations 12 4 1 Memory Interface 12 4 1 1 DDR3 12 4 1 2 DDR4 12 4 2 SPI Serial Flash 13 4 3 Transceivers 13 4 3 1 XCVR0 Interface 13 4 3 2 XCVR1 and XCVR3 Interface 14 4 3 3 XCVR2 Interface 15 4 3 4 XCVR Reference Clocks 16 4 4 Microsemi PHY VSC8575 17 4 4 1 Microsemi 1588v2 ZL30364GDG2 17 4 5 Power Monitoring 18 4 6 Programming 19 4 6 1 FTDI 19 4 7 System Reset 2...

Page 4: ...5 35 11 Appendix Power Monitoring 36 11 1 Prerequisites 36 11 2 Installing PowerMonitor 37 11 3 About Microsemi PowerMonitor 37 12 Appendix Errata 39 12 1 Errata Descriptions 39 12 1 1 Hot swapping is not supported on Programming headers J32 J29 PCIe CONN CON3 SFP cage J36 GPIO headers J7 J8 39 12 1 2 The VDDI3 Bank 3 supply voltage is higher than the Datasheet specification 39 ...

Page 5: ...face 14 Figure 8 XCVR1 and XCVR3 Interface 15 Figure 9 XCVR2 Interface 16 Figure 10 XCVR Reference Clocks 17 Figure 11 PHY Interface 18 Figure 12 Power Management 19 Figure 13 FTDI Interface 20 Figure 14 50 MHz Clock Oscillator 20 Figure 15 LED Interface 21 Figure 16 Switches Interface 22 Figure 17 SPST Interface 23 Figure 18 Silkscreen Top View 31 Figure 19 Silkscreen Bottom View 31 Figure 20 Sel...

Page 6: ... Evaluation Board Components 4 Table 3 Jumper Settings 8 Table 4 LEDs 9 Table 5 Test Points 10 Table 6 I O Voltage Rails 10 Table 7 Pin Details of 50 MHz Oscillator 20 Table 8 User LEDs 21 Table 9 Push Button Switches 21 Table 10 DIP Switches 22 Table 11 J34 FMC Connector Pinout 23 ...

Page 7: ... 1 Revision History The revision history describes the changes that were implemented in the document The changes are listed by revision starting with the most current publication 1 1 Revision 1 0 Revision 1 0 is the first publication of this document ...

Page 8: ...ble lists the contents of the PolarFire FPGA Evaluation Kit Note The PolarFire device is programmed using the on board FlashPro5 programmer The on board FlashPro5 programmer is used to develop and debug embedded applications using SoftConsole Identify or SmartDebug For more information see UG0726 PolarFire FPGA Board Design User Guide Table 1 Kit Contents Item Quantity PolarFire Evaluation Board p...

Page 9: ...l 16 deep 18 coefficient RO Built in µPROM modifiable at program time readable at run time for user data storage Digest integrity check for FPGA µPROM and sNVM Low power features Low device static power Low inrush current 3RODU LUH 3 03 76 96 3 7 86 PLQL FRQQHFWRU 6 0 5 07 61 E 6 2 DQN 7 DQN 3 2 DQN 5 07 E 6 2 DQN DQH 5 HEXJ V 6 2 DQN 0X 95 95 6 3 RQQHFWRU DQH 2Q RDUG 2VFLOODWRU 0 5 0 5 0 3 2 DQN ...

Page 10: ...d has 14 layers and it is manufactured using NElco SI material for top and bottom layers and FR4 dielectric material for inner layers The following labeled image highlights various components of the PolarFire Evaluation Board Figure 2 PolarFire Evaluation Board The following table lists the important components of the PolarFire Evaluation Board Table 2 PolarFire Evaluation Board Components Compone...

Page 11: ...and AE28 FPGA Programming and Debugging USB UART terminal J5 FTDI programmer interface to program the external SPI flash and the PolarFire device The J5 cable powers up the SmartFusion and the FTDI device that are required for power monitoring The J5 and J9 cables must be connected to power up the board SPI flash U44 and U45 Two 1 Gb SPI flash Micron MT25QL01GBBB8ESF 0SIT connected to SPI pins on ...

Page 12: ...5 A 128 Meg 8 8 chips are connected in Fly by topology with a 16 bit data bus for storing data bits For more information download the datasheet from https www micron com parts dram ddr3 sdram mt41k1g8sn 125 pc 00EED26F 83AE 4CE6 9A28 EB8B033361E8 DDR4 Memory U36 U42 U47 and U48 Four 8 Gb MT41K1G8SN 125 A 1G Meg 8 chips are connected in Fly by topology with a 32 bit data bus for storing data bits F...

Page 13: ...up the board connect the J5 USB cable to the host PC along with the 12 V supply If the USB cable is not connected the board does not power up irrespective of the 12 V supply The PolarFire Evaluation Board ships with a pre programmed bring up design LED toggling Install the software required for developing designs and set the jumpers for the pre programmed design For more information see Installati...

Page 14: ...nd DIP switches on the PolarFire Evaluation Board 3 2 1 Jumper Settings Connect the jumpers according to the settings specified in the following table Table 3 Jumper Settings Jumper Description Pin Default Setting J18 J19 J20 J21 J22 Jumpers to select the PolarFire JTAG or A2F JTAG Close pin 1 and 2 for programming the power sequence and monitoring chip through the FTDI Close pin 2 and 3 for progr...

Page 15: ...n 2 and 3 for remote power switching using the GPIO capability of the FT4232 chip Closed Open J12 Jumper to select the PolarFire VCCIO voltage VCCIO_HPC_ VADJ to 1 2V 1 5V 1 8V 2 5V or 3 3V Close pin 1 and 2 for 3 3 V Close pin 3 and 4 for 2 5 V Close pin 5 and 6 for 1 8 V Close pin 7 and 8 for 1 5 V Close pin 9 and 10 for 1 2 V Open Closed Open Open Open Table 4 LEDs LED Description DS3 Green 1 V...

Page 16: ...8V_ZL TP18 Test point to probe 5V voltage TP12 Test point to probe 3 3V voltage TP126 Test point to probe 1V voltage TP22 Test point to probe 1 5 V voltage for DDR3 TP8 Test point to probe 0 75 V TP12 1 5V current sensing test point TP115 Test point to probe 1 2 V voltage for DDR4 TP109 Test point to probe 0 6V voltage TP124 Test point to probe 1 8 V voltage TP23 Test point to probe 1 V voltage of...

Page 17: ...on the PolarFire Evaluation Board Figure 3 Voltage Rails in PolarFire Evaluation Board Bank 4 VCCIO_HPC_VADJ 3 3 V 2 5 V 1 8 V 1 5 V or 1 2 V Bank 5 VCCIO_HPC_VADJ 3 3 V 2 5 V 1 8 V 1 5 V or 1 2 V Bank 6 1P8V 1 8V Bank 7 1P2V_REG 1 2V VDD_XCVR_CLK VDD25_DUT 2P5V Table 6 I O Voltage Rails continued PolarFire Bank I O Rail Voltage 9 DWH 9 92B 1 5 B 9 37 7 37 7 37 7 9 9 9 736 5 75 0 5 63 736 5 75 63 ...

Page 18: ...d in Fly by topology Density 16 Gb Data rate DDR3 16 bit at 166 MHz clock rate The PolarFire Evaluation Board design uses the DDR3 and SSTL15 standards for the DDR3 interface The default board assembly available for the DDR3 standard has RC terminations Figure 4 DDR3 Memory Interface For more information see the Board Level Schematics document provided separately 4 1 2 DDR4 Four 8 Gb DDR4 SDRAM ch...

Page 19: ...MPF300TS 1FCG1152I device has 16 transceiver lanes These transceiver lanes can be accessed through the PCIe edge SFP SMA and FMC connectors on the board 4 3 1 XCVR0 Interface The XCVR0 interface has four lanes connected as follows Lanes 0 1 2 and 3 are directly routed to the PCIe connector TX pad trace AC coupling trace via to bottom layer trace PCIe connector pad RX pad trace via to Top layer tra...

Page 20: ...nes that are connected to FMC HPC connector and the signals are routed in the PCB as follows Lanes 0 to 7 are directly routed to the FMC HPC connector TX pad trace via to bottom layer trace FMC HPC connector pad RX pad trace via to Top layer trace PolarFire device pad The XCVR1 and XCVR3 reference clock is routed directly from the HPC connector to the PolarFire device 3RODU LUH DQH 5 DQH 5 DQH 5 D...

Page 21: ...e SMA connectors J41 P and J42 N RX pad trace via to Top layer trace SMA connectors J37 P and J38 N Lane 1 is connected to the SFP connector TX pad bottom trace via to Top layer SFP connector RX pad bottom trace via to Top layer SFP connector Lanes 2 and 3 are used for loopback testing This path is routed between the TX and RX pads with trace and two vias 3RODU LUH 95 DQH 5 95 DQH 5 95 DQH 5 95 DQ...

Page 22: ...0 mV maximum The following figure shows the XCVR2 interface of the PolarFire Evaluation Board Figure 9 XCVR2 Interface For information about the J46 jumper see Table 3 page 8 For more information see the Board Level Schematics document provided separately 4 3 4 XCVR Reference Clocks The XCVR supports the reference clocks connected as follows XCVR 1B 1C and 3C Reference clocks are connected to FMC ...

Page 23: ...IO and JTAG Device VSC8575 supports the IEEE 1588v2 timing implementation The ZL30364GDG2 chip provides the 125 MHz clock and reserved clocks to VSC8575 PHY Device ZL30364GDG2 is configurable through the SPI interface and connected to PolarFire device The key features of Microsemi PHY VSC8575 are Low Power IEEE 1588v2 Wide range of support SGMII QSGMII 4 4 1 Microsemi 1588v2 ZL30364GDG2 The PolarF...

Page 24: ...oltage rails The A2F200M3F 1FGG256I device is programmed through the FTDI interface and it supports the UART interface The A2F200M3F 1FGG256I device needs an external 20 MHz crystal frequency Key features of Microsemi A2F200M3F 1FGG256I are Microcontroller Subsystem MSS Analog Compute Engine ACE Programmable Analog Front End AFE For more information on how to monitor power on the board see Appendi...

Page 25: ... full speed 12 Mbps compatibility Two multi protocol synchronous serial engines MPSSE on channel A and channel B to simplify synchronous serial protocol USB to JTAG I2C SPI or bit bang design FTDI chip requires 1 8 V chip core voltage and 3 3 V I O voltage 6PDUW XVLRQ 3RZHU 0RQLWRULQJ 0RGXOH Q5XVK XUUHQW LPLWHU 0LQL 86 RQQ 9 736 4 9 736 4 86 9 B 9 9 9 7 3257 9 B 9 9 B 9 6PDUW XVLRQ 6 B6 6 B6 6 B6 ...

Page 26: ...ire PLL can be configured to generate a wide range of high precision clock frequencies The following table provides package and pin details of the 50 MHz oscillator The following figure shows the 50 MHz clock oscillator interface Figure 14 50 MHz Clock Oscillator For more information see the Board Level Schematics document provided separately 4 9 User Interface The PolarFire Evaluation Board has u...

Page 27: ...o the PolarFire device The following table lists the on board push button switches Table 8 User LEDs PolarFire Evaluation Board Pin PolarFire FPGA Pin Number PolarFire FPGA Pin Name Bank LED7 D25 HSIO70PB6 CCC_SE_PLL1_OUT1 Bank 6 LED6 C26 HSIO70NB6 Bank 6 LED5 B26 HSIO71NB6 Bank 6 LED4 F22 HSIO64NB6 Bank 6 LED11 H21 HSIO36NB6 Bank 6 LED10 H22 HSIO60NB6 Bank 6 LED9 F23 HSIO62PB6 DQS CCC_SE_PLL0_OUT...

Page 28: ...4 DIP Switches SPST The SW11 DIP switch has eight connections to the PolarFire device The following table lists the on board DIP switches Table 10 DIP Switches PolarFire Evaluation Board Pin PolarFire FPGA Pin Number PolarFire FPGA Pin Name Bank DIP1 H23 HSIO60PB6 Bank 6 DIP2 D21 HSIO48NB6 Bank 6 DIP3 H24 HSIO61NB6 Bank 6 DIP4 C22 HSIO50PB6 DQS Bank 6 DIP5 B21 HSIO49NB6 Bank 6 DIP6 G20 HSIO41PB6 B...

Page 29: ...ication 4 9 6 FMC Connector HPC J34 The PolarFire GPIO XCVR1 and XCVR3 signals are routed to the FMC connector J34 for application development The following table provides the J34 FMC pinout details Table 11 J34 FMC Connector Pinout FMC Pin Number J34 FMC Net Name PolarFire Pin Number PolarFire Pin Name A2 HPC_SERDES_1_RX1_P P29 XCVR_1_RX1_P A3 HPC_SERDES_1_RX1_N P30 XCVR_1_RX1_N A6 HPC_SERDES_1_R...

Page 30: ... R28 XCVR_1B_REFCLK_N B12 HPC_SERDES_3_RX3_P L31 XCVR_3_RX3_P B13 HPC_SERDES_3_RX3_N L32 XCVR_3_RX3_N B16 HPC_SERDES_3_RX2_P K29 XCVR_3_RX2_P B17 HPC_SERDES_3_RX2_N K30 XCVR_3_RX2_N B20 HPC_SERDES_3_INT_REFCLK_P J27 XCVR_3A_REFCLK_P B21 HPC_SERDES_3_INT_REFCLK_N J28 XCVR_3A_REFCLK_N B28 HPC_DP8_C2M_P H29 XCVR_3C_REFCLK_P B29 HPC_DP8_C2M_N H30 XCVR_3C_REFCLK_N B32 HPC_SERDES_3_TX3_P M33 XCVR_3_TX3_...

Page 31: ... D14 HPC_LA09_P_B2 L17 GPIO30PB2 D15 HPC_LA09_N_B2 M17 GPIO30NB2 D17 HPC_LA13_P_B2 H14 GPIO3PB2 D18 HPC_LA13_N_B2 G14 GPIO3NB2 D20 HPC_LA17_CC_P_B2 F8 GPIO9PB2 CLKIN_S_6 D21 HPC_LA17_CC_N_B2 F7 GPIO9NB2 D23 HPC_LA23_P_B2 C7 GPIO12PB2 D24 HPC_LA23_N_B2 B7 GPIO12NB2 D26 HPC_LA26_P_B2 G12 GPIO18PB2 D27 HPC_LA26_N_B2 G11 GPIO18NB2 D29 HPC_TCK D30 HPC_TDI D31 HPC_TDO D33 HPC_TMS D34 HPC_TRST_L E2 HPC_H...

Page 32: ...5 F1 HPC_PG_M2C_B6 C19 HSIO45NB6 F4 HPC_HA00_CC_P_B4 W5 GPIO195PB4 F5 HPC_HA00_CC_N_B4 Y5 GPIO195NB4 F7 HPC_HA04_P_B4 AB9 GPIO183PB4 F8 HPC_HA04_N_B4 AA8 GPIO183NB4 F10 HPC_HA08_P_B4 AB7 GPIO179PB4 F11 HPC_HA08_N_B4 AB6 GPIO179NB4 F13 HPC_HA12_P_B4 T7 GPIO218PB4 F14 HPC_HA12_N_B4 U7 GPIO218NB4 F16 HPC_HA15_P_B4 V8 GPIO198PB4 F17 HPC_HA15_N_B4 V7 GPIO198NB4 F19 HPC_HA19_P_B4 AB4 GPIO177PB4 F20 HPC_...

Page 33: ... G19 HPC_LA16_N_B2 D11 GPIO26NB2 DQS G21 HPC_LA20_P_B2 B9 GPIO25PB2 G22 HPC_LA20_N_B2 A9 GPIO25NB2 G24 HPC_LA22_P_B2 D8 GPIO14PB2 DQS G25 HPC_LA22_N_B2 C8 GPIO14NB2 DQS G27 HPC_LA25_P_B2 J11 GPIO4PB2 G28 HPC_LA25_N_B2 H11 GPIO4NB2 G30 HPC_LA29_P_B2 B10 GPIO28PB2 G31 HPC_LA29_N_B2 A10 GPIO28NB2 G33 HPC_LA31_P_B2 E7 GPIO15PB2 G34 HPC_LA31_N_B2 E8 GPIO15NB2 G36 HPC_LA33_P_B2 H7 GPIO8PB2 DQS G37 HPC_L...

Page 34: ... H37 HPC_LA32_P_B2 E1 GPIO245PB2 CCC_SW_CL KIN_S_1 H38 HPC_LA32_N_B2 D1 GPIO245NB2 J2 HPC_CLK3_BIDIR_P_B4 AD4 GPIO180PB4 CLKIN_W_6 C CC_NW_CLKIN_W_6 CCC_ NW_PLL0_OUT1 J3 HPC_CLK3_BIDIR_N_B4 AD5 GPIO180NB4 J6 HPC_HA03_P_B4 AB11 GPIO186PB4 J7 HPC_HA03_N_B4 AB10 GPIO186NB4 J9 HPC_HA07_P_B4 AB14 GPIO185PB4 J10 HPC_HA07_N_B4 AC13 GPIO185NB4 J12 HPC_HA11_P_B4 V13 GPIO203PB4 J13 HPC_HA11_N_B4 W13 GPIO203...

Page 35: ...IO184PB4 K14 HPC_HA10_N_B4 AC12 GPIO184NB4 K16 HPC_HA17_CC_P_B4 T9 GPIO219PB4 CLKIN_W_3 C CC_SW_CLKIN_W_3 K17 HPC_HA17_CC_N_B4 T8 GPIO219NB4 K19 HPC_HA21_P_B4 W10 GPIO200PB4 K20 HPC_HA21_N_B4 Y10 GPIO200NB4 K22 HPC_HA23_P_B4 AB2 GPIO176PB4 K23 HPC_HA23_N_B4 AB1 GPIO176NB4 K25 HPC_HB00_CC_P_B5 G2 GPIO243PB5 CLKIN_W_0 C CC_SW_CLKIN_W_0 K26 HPC_HB00_CC_N_B5 G1 GPIO243NB5 K28 HPC_HB06_CC_P_B5 H2 GPIO2...

Page 36: ...Pin List UG0747 User Guide Revision 1 0 30 5 Pin List For information on all of the package pins on the PolarFire device see Package Pin Assignment Table ...

Page 37: ...onent Placement The following figure shows the placement of various components on the PolarFire Evaluation Board silkscreen Figure 18 Silkscreen Top View The following figure shows the bottom view of the PolarFire Evaluation Board silkscreen Figure 19 Silkscreen Bottom View ...

Page 38: ...Demo Design UG0747 User Guide Revision 1 0 32 7 Demo Design To be updated ...

Page 39: ...Manufacturing Test UG0747 User Guide Revision 1 0 33 8 Manufacturing Test To be updated ...

Page 40: ...Appendix Running the Demo Design UG0747 User Guide Revision 1 0 34 9 Appendix Running the Demo Design To be updated ...

Page 41: ...d is successfully set up the LEDs start glowing 4 On the host PC start the FlashPro software 5 Click New Project to create a new project 6 In the New Project window do the following and click OK Enter a project name Select Single device as the programming mode 7 Click Configure Device 8 Click Browse and select the xxxxxxxxxxxxxx stp file from the Load Programming File window Note The programming f...

Page 42: ... GPSS VDD25 Power supply for corner phase locked loop 8 PLLs and secure non volatile memory sNVM These are tied together at the package level to keep the noise on the stand alone PLLs low Monitors Flash Freeze power when the PolarFire device is in Flash Freeze mode Powers down the board if voltage threshold violations are observed on any power rail The analog computing engine block in the SmartFus...

Page 43: ... 3 From the Start menu click PowerMonitor The COMPort SetUp dialog opens 4 Select the highest numbered COM port and click Connect The PowerMonitor GUI appears on the host PC 11 3 About Microsemi PowerMonitor The following figure shows the PowerMonitor GUI Figure 22 PowerMonitor GUI The PowerMonitor GUI has the following panes CurrentMonitor This pane displays the current and power measured on VDD ...

Page 44: ...ram Use this button to display the data in the CurrentMonitor pane as a histogram Pie Chart Use this button to display the data in the CurrentMonitor pane as a pie chart Show Log Use this button to see a file with all power monitor program actions RMT PWR ON OFF Use this button to power up and power down the board ...

Page 45: ... supported on Programming headers J32 J29 PCIe CONN CON3 SFP cage J36 GPIO headers J7 J8 This restriction applies to Rev B and C of the board 12 1 2 The VDDI3 Bank 3 supply voltage is higher than the Datasheet specification Bank 3 VDDI3 and all circuits connected to Bank 3 have supply voltage of 3 3 V User should not use the supply voltage of 3 3 V for Rev B board of Bank 3 This is addressed in th...

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