Board Components and Operations
UG0747 User Guide Revision 1.0
12
4
Board Components and Operations
This section describes the key components of the PolarFire Evaluation board and important board
operations. For device datasheets, visit
www.microsemi.com/products/fpga-soc/design-resources/dev-
kits/polarfire-kits
.
4.1
Memory Interface
GPIO and HSIO bank I/Os for DDR3 and DDR4 are available in the PolarFire device. In addition to
dedicated I/Os, regular I/Os can also be used to connect to other memory devices.
4.1.1
DDR3
Two 8 Gb DDR3 SDRAM chips are provided to serve as flexible volatile memory for user applications.
The DDR3 interface is implemented in HSIO bank 1.
The DDR3 SDRAM specifications for the PolarFire device are:
•
MT41K1G8SN-125: (128 Meg × 8 × 8)
•
Two chips are connected in Fly-by topology
•
Density: 16 Gb
•
Data rate: DDR3 16-bit at 166 MHz clock rate
The PolarFire Evaluation Board design uses the DDR3 and SSTL15 standards for the DDR3 interface.
The default board assembly available for the DDR3 standard has RC terminations.
Figure 4 •
DDR3 Memory Interface
For more information, see the Board-Level Schematics document (provided separately).
4.1.2
DDR4
Four 8 Gb DDR4 SDRAM chips are provided to serve as flexible volatile memory for user applications.
The DDR4 interface is implemented in HSIO bank 0 and Bank 7.
The DDR4 SDRAM specifications for the PolarFire device are:
•
MT40A1G8WE-083E:B
•
Quantity: Four chips are connected in Fly-by topology
•
Density: 32 Gb
•
Data rate: DDR4 32-bit at 166 MHz clock rate
The PolarFire Evaluation Board design uses the DDR4 and POD12 standards for the DDR4 interface.
The default board assembly available for the DDR4 standard has RC terminations.
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