Universal Serial Bus OTG Controller
UG0331 User Guide Revision 15.0
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10.3.3
USB OTG Controller Clocks and Resets
The following conditions are to be considered in the design for clocks and resets while using the USB
OTG controller:
•
In order to operate the USB OTG controller correctly with the external USB PHY device, the MSS
FCLK and AHB CLK must be configured to run at greater than 30 MHz.
•
In order to reset the external USB PHY, it is necessary to use an MSS GPIO port. Firmware resets
the USB PHY whenever there is a USB controller reset done by the USB soft reset register settings.
•
The USB controller resets on power-up and is held in reset until it is enabled. The USB controller can
be reset by writing to USB_SOFTRESET field of the SOFTRESET_REG at address 0x40038048,
located in the SYSREG block. The USB firmware drivers implements this feature.
At power-up this bit is asserted as 1. This keeps the USB controller in a reset state. If the bit is set to 0,
the USB controller is allowed to become active. If USB_SOFTRESET is 0, the USB controller could still
be held in reset by other system reset sources.
10.3.4
Programmability
10.3.4.1 Memory Map
The address space of the USB OTG controller in SmartFusion2 is from 0x40043000 to 0x40043FFF. All
the USB OTG FIFO registers are residing in this address space.
10.3.4.2 USB OTG Controller Registers Map
This section describes the register map; bit description of various categories of registers in the USB
controller. In addition, System Registers that are applicable to USB are described in this section. This
provides programmers information for firmware development. Microsemi recommends using the drivers
provided in the tool set for application development.
The Register set in the USB controller consists of the following categories:
•
Common Registers: Provide control and status for the USB controller.
•
Indexed Registers: Provide control and status for the currently selected end point (host or
peripheral).
•
FIFO Registers: Provide access to end point FIFOs in the USB controller.
•
Control and Configuration Registers: Provide additional device status and control.
•
Non-Indexed End Point Control/Status Registers: Are accessible independently for every endpoint,
whereas indexed registers are shared by endpoints. These cover EP0, EP1, EP2, EP3, and EP4.
•
Extended Registers: Provides details on additional registers that control and affect the operation of
the USB controller.
•
DMA Registers: Provide control and status of built-in DMA.
•
Multipoint Control and Status Registers: Details additional control and status registers that relate to
the multipoint option. These registers are required and have relevance in Host mode only.
•
LPM Registers: These correspond to LPM.
•
USB System Registers: Are SmartFusion2 system registers that are associated with USB.
Table 197 •
SOFTRESET_REG Bit for USB Controller Soft Reset
Register Name
Address
Bit
Number Name
Reset
Value
Function
0x40038048 14
USB_SOFTRESET 0x1
Controls reset input to the USB
controller
0: Release USB controller from reset
1: Keep USB controller in reset (reset
value)