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Mercury 2 Reference Manual 

v1.0 August 2, 2019 

© 2019 MicroNova LLC 

www.micro-nova.com 

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FTDI channel A is connected directly to the FPGA configuration pins, FPGA_PROG (to initiate an FPGA 
configuration cycle) and FPGA_DONE (to read back the FPGA configuration status). FTDI channel A is also 
connected to a digital mux (U5) which is switched between either: the SPI F

lash (U6), or the FPGA’s JTAG port. 

The digital mux is controlled via FTDI channel A. 

MicroNova provides an open-source programmer utility called 

mercury2_prog

. The Mercury 2 Programmer utility 

is a command-line application written in C, and built as a native app for both Linux and Windows. The utility 

communicates with the FT2232H via FTDI’s D2XX driver. The utility writes the specified FPGA bitstream file to the 

SPI Flash. It is also capable of reading back from the SPI Flash, or erasing the entire SPI Flash. Before accessing 
the SPI Flash, the FT2232H asserts the FPGA_PROG pin, during which time the FPGA is kept in reset and 
prevented from reading from the SPI Flash. After accessing the SPI Flash, the FT2232H de-asserts the 
FPGA_PROG pin, releasing control of the SPI Flash to the FPGA. The FPGA attempts to boot from the SPI Flash, 
and asserts the FPGA_DONE pin if it has successfully booted. 

For most applications, the provided on-board USB port is suitable. For users who require it, the Mercury 2 board 
also contains an auxiliary JTAG header wired directly to the Artix-7 FPGA (J8). The JTAG port is a 2x3 header with 
0.05 inch (1.27mm) spacing. This port may be useful if you would like to connect to the Artix-7 directly using a 
Xilinx JTAG cable (such as the Platform Cable USB II), or if you want to program the FPGA directly via a 
microcontroller (see Xilinx XAPP058

: In-System Programming Using an Embedded Microcontroller

).  

 

 

 

 

 

 

 

Figure 7:

 

Direct JTAG port

 

Figure 6:

 

FTDI-to-FPGA configuration interface

 

Summary of Contents for Mercury 2

Page 1: ...er The board is also equipped with a 10 100 Ethernet PHY for network connectivity The complete schematics for Mercury 2 are available on our website along with open source USB programmer apps for Wind...

Page 2: ...Mercury 2 Reference Manual v1 0 August 2 2019 2019 MicroNova LLC www micro nova com 2 of 9 Figure 2 Simplified Block Diagram Figure 3 DIP Pin Distribution...

Page 3: ...Programming status LED RED 5 D1 Power LED GREEN 6 Optional ESP8266 ESP 11 Wi Fi Module header connection 7 Xilinx XADC Analog Input Connection 8 Optional JTAG header See Configuration section for det...

Page 4: ...ation CONFIGURATION At power on the Artix 7 FPGA must be configured before it can perform any useful function The FPGA is essentially a blank slate of memory cells and programmable circuit interconnec...

Page 5: ...e SPI Flash or erasing the entire SPI Flash Before accessing the SPI Flash the FT2232H asserts the FPGA_PROG pin during which time the FPGA is kept in reset and prevented from reading from the SPI Fla...

Page 6: ...interfacing with 5V logic consider whether the device requires 5V CMOS logic levels or 5V TTL logic levels The level shifting logic onboard Mercury 2 is made to handle 5V inputs However Mercury s I O...

Page 7: ...default configuration of Mercury 2 uses a 4Mbit SRAM part ISSI IS61WV5128BLL 10TLI but 8Mbit and 16Mbit SRAM modules are available as a build to order option Note that the upper address bits A 20 19...

Page 8: ...ther channel can be driven by a range of inputs including the direct coax input as well as aux inputs on direct I O pins 3 8 The XADC can also be used to monitor the FPGA internal temperature and powe...

Page 9: ...C driver and sine wave generator project ETHERNET PHY Mercury 2 includes a SMSC LAN8720A 10 100 Ethernet PHY 0 1 header holes are provided on Mercury 2 for connecting an optional RJ 45 Ethernet jack w...

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