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tn2916_boot_from_nand_omap2420.fm - Rev. D 6/07 EN
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©2006 Micron Technology, Inc. All rights reserved.
TN-29-16: Boot-from-NAND with the TI OMAP2420 Processor
Stage 1: Processor ROM Code
Code Shadowing to the OMAP Processor SRAM
After the NAND Flash device configuration has been verified and the bad blocks have
been checked, the process of copying (shadowing) the X-Loader from the NAND Flash
device to the internal SRAM of the OMAP2420 processor begins.
First, the ROM code reads bytes 1 through 4 of the X-Loader to determine the size of the
file; then it reads bytes 5 through 8 of the X-Loader, which contain the destination
address in SRAM where the X-Loader will be shadowed (see Figure 6 on page 8). The
ROM code then shadows the X-Loader from the NAND Flash device to the OMAP2420
processor SRAM (see Figure 4), and finally, the system jumps to the SRAM address where
the first byte of the X-Loader is stored.
Figure 4:
Shadowing X-Loader Code from NAND Flash to SRAM
Error Correction Code
The ROM code contains error correction code and checks for errors in the X-Loader. The
ECC scheme is a Hamming code capable of detecting 2-bit errors and correcting one
1-bit error per 512 bytes.
• When a 1-bit error is detected in a 512-byte sector, the ROM code will use the ECC to
correct the error, and the boot process will continue from that block.
• When a 2-bit error is detected in a 512-byte sector, the ROM code will skip this block
and attempt to boot from the next block.
• When an error of 3 bits or more is detected, effects on the system may vary and may
include hanging.
Figure 7 on page 9 depicts how the X-Loader, bad block marking, and ECC are stored in a
typical page of the MT29F1G08ABB NAND Flash device programmed for boot-from-
NAND in an OMAP2420-based system.
Micron NAND Flash
U-Boot
U-Boot
environment data
OS kernel
Micron DRAM
OMAP2420 processor ROM
OMAP2420 processor SRAM
ROM process
Block 0 = X-Loader
Block 1 = X-Loader
Block 2 = X-Loader
Block 3 = X-Loader
X-Loader
X-Loader
ROM code
File system
