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tn2916_boot_from_nand_omap2420.fm - Rev. D  6/07 EN

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©2006 Micron Technology, Inc. All rights reserved.

 TN-29-16: Boot-from-NAND with the TI OMAP2420 Processor

Stage 1: Processor ROM Code

If the device ID of the NAND Flash is not supported by the ROM, an attempt is made to 
determine the configuration of the NAND Flash device by performing a READ ID2 oper-
ation. Contact your Micron representative for READ ID2 operation details. If both the 
READ ID and READ ID2 operations fail, the ROM code performs a software reset on the 
system.

Stage 1: Processor ROM Code

Stage 1 is the execution of the OMAP2420 processor ROM code. This ROM code cannot 
be modified by the system designer. Only NAND Flash devices supported by the ROM 
code can be used for boot-from-NAND with the OMAP2420 device. If the ROM code 
does not support a particular NAND Flash device, contact a Texas Instruments represen-
tative to determine if additional ROM code is available that will support the Micron 
NAND Flash device.

After a power-on-reset is initiated, the ROM code reads the SYS.BOOT register to deter-
mine the memory interface configuration and programs the general-purpose memory 
controller (GPMC) accordingly. Then the ROM code issues a RESET (FFh) command (see 
Figure 2) to the NAND Flash device, followed by a READ ID (90h) command (see Figure 3 
on page 5). The READ
 ID operation enables the OMAP2420 processor to determine how 
the NAND Flash device is configured and whether this device is supported by the ROM 
code.

Table 3 shows the required SYS.BOOT register settings to support boot-from-NAND. 
Micron NAND Flash devices are available in both x8 and x16 configurations; the Micron 
NAND Flash device referenced in this technical note, MT29F1G08ABB, has a x8 inter-
face.

Table 2: 

Micron NAND Flash Devices Supported by the OMAP2420 Processor

Micron Part Number

Density

Device ID

Bus Width

Page Size 

(bytes)

MT29F1G08ABB

1Gb

A1h

x8

2,112

MT29F1G16ABB

1Gb

B1h

x16

2,112

MT29F2G08AAD

2Gb

AAh

x8

2,112

MT29F2G16AAD

2Gb

BAh

x16

2,112

Table 3: 

SYS.BOOT Register

SYS.BOOT[3:0]

Device Type

3

2

1

0

1

1

0

0

x8 NAND Flash

1

1

0

1

x16 NAND Flash

Summary of Contents for MT29F1G08ABB

Page 1: ...t and high performance NAND Flash is beginning to make its way into more complex embedded systems where NOR Flash has dominated in the past for example in mobile phones In complex embedded systems one...

Page 2: ...r daughter card Menelaus ES 2 0 S N 750 0006 Rev C The boot from NAND concepts discussed are OS independent however the Linux OS is used as an example in some explanations Note that secure booting via...

Page 3: ...or ROM can be used for the boot process see Table 2 on page 4 Stage 2 Bootstrap X Loader is an example of stage 2 bootstrap code The X Loader code is stored in the NAND Flash and the ROM code copies i...

Page 4: ...n tative to determine if additional ROM code is available that will support the Micron NAND Flash device After a power on reset is initiated the ROM code reads the SYS BOOT register to deter mine the...

Page 5: ...he ROM code expects the X Loader to be in block 0 1 2 or 3 of the NAND Flash device and can use any of these blocks in the boot process After the NAND Flash device config uration has been determined t...

Page 6: ...em jumps to the SRAM address where the first byte of the X Loader is stored Figure 4 Shadowing X Loader Code from NAND Flash to SRAM Error Correction Code The ROM code contains error correction code a...

Page 7: ...the system designer Figure 6 on page 8 illustrates how the Boot_image bin code is laid out in the NAND Flash 1 Compile the X Loader source code into an executable format The example in Figure 5 on pag...

Page 8: ...BB NAND Flash See Writing Binary Images to NAND Flash with Limited OST Tools Support on page 12 for instructions regard ing alternatives Figure 6 X Loader Layout Develop code to format image for 2KB p...

Page 9: ...o DRAM see Figure 8 Then the system jumps to the address in DRAM where the first byte of the U Boot code resides Figure 8 Shadowing U Boot Code from NAND Flash to DRAM Byte 2 111 Bad Block Marking Byt...

Page 10: ...map must be configured to support boot from NAND U Boot must contain NAND Flash support such that it can read and write to the NAND Flash device U Boot environment data should be written such that it...

Page 11: ...em The final stage of the boot process involves the initial execution of the OS The operating system kernel is stored in NAND Flash and shadowed to DRAM for execution as described in the stage 3 boot...

Page 12: ...Flash devices In these cases it is necessary to develop an alternative method for loading the boot code into the NAND Flash device A workstation similar to the one shown in Figure 11 is required In a...

Page 13: ...with the TI OMAP2420 Processor Writing Binary Images to NAND Flash with Limited OST Tools Run the U Boot Program 1 Use JTAG to load the U Boot program into the Micron DRAM see Figure 12 The U Boot pro...

Page 14: ...nal window 2 Place the X Loader image in the TFTP server 3 Write a copy of the X Loader file to the DRAM using the U Boot program 4 Erase the area in the NAND Flash where the X Loader will reside 5 Co...

Page 15: ...e NAND Flash 1 Place the U Boot file in the TFTP server 2 Write a copy of the U Boot file to the DRAM using the U Boot program 3 Erase the area in the NAND Flash where U Boot will reside 4 Copy the U...

Page 16: ...the TFTP server 2 Write a copy of the OS kernel file to the DRAM using the U Boot program 3 Erase the area in the NAND Flash where the OS kernel will reside 4 Use the U Boot program to copy the OS ke...

Page 17: ...file system file in the TFTP server 2 Write the root file system file to the DRAM using the U Boot program 3 Erase the area in the NAND Flash where the file system will reside 4 Copy the file system f...

Page 18: ...single program opera tion Verify that the X Loader U Boot OS kernel and root file system were programmed correctly by performing a read verify to compare the NAND Flash contents against the original b...

Page 19: ...Revised description Code Shadowing to the OMAP Processor SRAM on page 6 Changed SDRAM to SRAM Rev C 7 06 Figure 1 on page 3 Updated content Boot Stages on page 3 and Stage 1 Processor ROM Code on page...

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