Figure 3-28. e.MMC Memory Schematic
0.1uF
10V
0402
C141
VDDSDMMC0
GND
VDDSDMMC0
VDD_3V3
SDMMC0_DAT0_PA3
SDMMC0_DAT1_PA4
SDMMC0_DAT2_PA5
SDMMC0_DAT3_PA6
SDMMC0_DAT4_PA7
SDMMC0_DAT5_PA8
SDMMC0_DAT6_PA9
SDMMC0_DAT7_PA10
SDMMC0_CMD_PA1
SDMMC0_CK_PA0
SDMMC0_RSTN_PA2
i
EMMC
Matched Net Lengths [Tolerance = 0.25mm]
47k
0402
5%
R121
47k
0402
5%
R122
47k
0402
5%
R123
47k
0402
5%
R124
47k
0402
5%
R125
47k
0402
5%
R126
47k
0402
5%
R127
47k
0402
5%
R128
47k
0402
5%
R130
SDMMC0_DS_PA11
GND
0.1uF
10V
0402
C136
4.7uF
10V
0402
C137
GND
4.7uF
10V
0402
C139
0.1uF
10V
0402
C138
4.7uF
10V
0402
C140
eMMC
10k
0402
1%
R129
22R
0402
1%
R131
22R
0402
1%
R132
47k
0402
5%
R135
GND
DAT0
A3
DAT1
A4
DAT2
A5
DAT3
B2
DAT4
B3
DAT5
B4
DAT6
B5
DAT7
B6
VDDI
C2
VSSQ C4
VCCQ C6
VCC E6
VSS E7
VSSQ N5
VCC F5
VSS G5
VSS H10
VSS K8
VCC K9
VCCQ M4
CMD
M5
CLK
M6
VSSQ N2
VCCQ N4
VCCQ P3
VSSQ P4
VCCQ P5
VSSQ P6
RSTn
K5
VCC J10
DS
H5
VSS A6
VSS J5
S40FC004C1B1C00000
U10
SDMMC0_DS
VDDI
SDMMC0_RSTN_PA2
SDMMC0_CMD_PA1
SDMMC0_DAT3_PA6
SDMMC0_DAT4_PA7
SDMMC0_DAT5_PA8
SDMMC0_DAT6_PA9
SDMMC0_DAT7_PA10
VLDO1
0R
0603
R133
50
Ω
± 10% single-ended trace impedance
Routing top or bottom
Place R117 close to MPU
Place R118 close to eMMC device
Table 3-14. e.MMC NAND Flash Signal Descriptions
PIO
Signal Name
Shared PIO
Signal Description
PA0
SDMMC0_CK_PA0
–
e.MMC clock signal
PA1
SDMMC0_CMD_PA1
–
e.MMC command line
PA2
SDMMC0_RSTN_PA2
–
e.MMC reset signal
PA3
SDMMC0_DAT0_PA3
–
e.MMC data line 0
PA4
SDMMC0_DAT1_PA4
–
e.MMC data line 1
PA5
SDMMC0_DAT2_PA5
–
e.MMC data line 2
PA6
SDMMC0_DAT3_PA6
–
e.MMC data line 3
PA7
SDMMC0_DAT4_PA7
–
e.MMC data line 4
PA8
SDMMC0_DAT5_PA8
–
e.MMC data line 5
PA9
SDMMC0_DAT6_PA9
–
e.MMC data line 6
PA10
SDMMC0_DAT7_PA10
–
e.MMC data line 7
PA11
SDMMC0_DS_PA11
–
e.MMC data strobe
To enable booting on e.MMC, the PA14 I/O must be grounded. A circuitry is available on the SAMA7G54-EK board to
enable/disable boot from e.MMC. See
3.3.3
Octal Serial Flash
The SAMA7G54-EK board features one Quad Serial Peripheral Interface (QSPI) memory MX66LM1G45GXDI00.
The QSPI is a synchronous serial data link that provides communication with external devices in Host mode.
The QSPI can be used in SPI mode to interface to serial peripherals (such as ADCs, DACs, LCD controllers, CAN
controllers and sensors), or in Serial Memory mode to interface to serial Flash memories. Octal SPI mode is then
used.
Using the QSPI, the system executes code directly from a serial Flash memory (XIP) without code shadowing to
RAM. The serial Flash memory mapping is seen in the system as other memories such as ROM, SRAM, DRAM,
embedded Flash memory, etc.
SAMA7G54-EK
Function Blocks
©
2022 Microchip Technology Inc.
and its subsidiaries
User Guide
DS50003273A-page 37
