...........continued
Pin Name
Type
Used for
MIPI_CLK_[P-N]
Input
MIPI differential input clock lanes
MIPI_DP[0-1]
Input
MIPI differential input data lanes
MIPI_REXT
Input
MIPI calibration
3.2.3
Clock Circuitry
The embedded MPU generates the required clocks based on two oscillators: one slow clock (SLCK) oscillator
running at 32.768 kHz and one main clock oscillator running at 24 MHz.
3.2.3.1
Main Clock Circuitry
The main clock oscillator is implemented with a MEMS (Micro Electro-Mechanical System) device DSC1001.
For evaluation purposes, the user can mount a crystal instead of the MEMS, using the PCB footprint reservation (Y3).
In that case, remove resistors R34 and R36, populate resistors R37 and R40 and populate capacitors C76 and C81
with the appropriate load capacitance for the selected crystal.
Figure 3-11. Processor Main Clock Schematic
GND
GND
XIN
VDD_3V3
XOUT
GND
XIN
24MHz clock
24MHz 18pF
ABM8G-24.000MHZ-18-D2Y-T
Y3
24MHz
STB 1
GND
2
OUT 3
VDD
4
Y2
20pF
0402
C76
20pF
0402
C81
0.1uF
10V
0402
C64
51R
0402
1%
R34
0402
R37
0402
R40
XIN_24M
XOUT_24M
1M
0402
1%
R39
0402
R36
XOUT
GND
TP16
OSC_STBY
3.2.3.2
Slow Clock Circuitry
The slow clock oscillator is implemented with a NX2012SA-32.768K crystal device.
For evaluation purposes, the user can mount instead a MEMS (Micro Electro-Mechanical System
DSC6003MA3B-032K768), using the PCB footprint reservation (Y4). In that case, remove crystal Y1 and capacitors
C66 and C72, and populate resistor R38 and capacitor C77 with the appropriate MEMS (Y4).
SAMA7G54-EK
Function Blocks
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2022 Microchip Technology Inc.
and its subsidiaries
User Guide
DS50003273A-page 18
