3.
PL485-EK Board
3.1
Overview
This section summarizes the PL485-EK board design. It introduces system-level concepts, such as power supply,
MCU, PLC coupling, peripherals and board interfaces.
Figure 3-1. PL485-EK Board Description
mikroBUS Connector (J8)
I2S Connector (J9)
RESET Button (SW1)
JTAG/SWD Connector (J15)
USB Device Connector (J5)
JLINK SAM3U (U5)
3.3V Buck Converter (U3)
Xplained PRO connector (J6)
5V Buck Converter (U2)
Test Point 3.3V (TP10)
Test Point 5V (TP6)
Test Point GND (TP9)
Test Point PLC Signal (TP16)
Test Point GND (TP8)
DC Input Connectors (J2 & J3)
AC Coupler Connector (J4)
Xplained PRO PWR connector (J7)
ERASE Pin Header (J1)
CDC Disable Pin Header (J13)
JLINK Disable Pin Header (J14)
PL485 (U1)
JLINK USB Connector (J12)
JLINK 3.3V LDO Converter (U7)
PLC Coupling
PLC Rejection Filter
PLC Signal and
3.2
Features List
The PL485-EK board includes the following features:
• PL485 SOC:
– MCU Core:
• ARM Cortex-M4 running at up to 100 MHz
• Memory Protection Unit (MPU)
• DSP instruction set
• Floating-Point Unit (FPU)
• Thumb
®
-2 instruction set
• Instruction and Data Cache Controller with 2 Kbytes cache memory
– Memories:
• Up to 512 Kbytes of embedded Flash
• Up to 176 Kbytes of embedded SRAM
PL485-EK
PL485-EK Board
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2020 Microchip Technology Inc.
User Guide
DS50002954B-page 6
