The PL485 embeds a PL360, a multi-protocol modem for Power Line Communication, and it also embeds a
SAMG55, a Cortex-M4 CPU with an FPU (floating point unit). This flexible architecture allows implementation of
standard and customized PLC solutions.
shows the different components of PL485 Schematic.
Figure 3-4. PL485
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
D
D
C
C
B
B
A
A
PL485.SchDoc
File:
PA0
H1
PA1
K1
PA2
H2
PA3
J2
PA4
J1
PA5
K2
PA6
L3
PA7/XIN32
J3
PA8/XOUT32
K3
PA9
G9
PA10
H11
PA11
H10
PA12
J11
PA13
J10
PA14
J9
PA15
L4
PA16
K4
PA17
J8
PA18
K8
PA19
H8
PA20
K9
PA21/DM
L6
PA22/DP
K6
PA23
L5
PA24
F5
PA25
F3
PA26
F6
PA27
F8
PA28
F7
PA29
G5
PA30
G7
PA31
F1
MPL485A-I/AJA
U1A
PB0
K10
PB1
L8
PB2
L9
PB3
K11
PB4
G2
PB5
G10
PB6
F10
PB7
F9
PB8/XOUT
G11
PB9/XIN
F11
PB10
G8
PB11
H9
PB12
J4
PB13
F4
PB14
G1
PB15
F2
MPL485A-I/AJA
U1B
ADVREF
K7
MCU_TST
H4
MCU_NRST
H3
JTAGSEL
G3
MPL485A-I/AJA
U1C
PL_VZC
A2
PL_PA1
A3
PL_PA2/TRACESWO
D3
PL_PA3
E6
PL_PA4/SWDIO
D2
PL_PA5/SWCLK
E2
PL_PA0
E5
PL_PA6/NPCS0
G6
PL_PA7/SPCK
G4
PL_PA8/MOSI
E7
PL_PA9/MISO
E8
PL_XIN
B2
PL_XOUT
B1
PL_AGC
B9
PL_TXRX1
A10
PL_TXRX0
A9
PL_EMIT3
C10
PL_EMIT2
C11
PL_EMIT1
D10
PL_EMIT0
D11
PL_VIN
A7
PL_VREFP
B7
PL_VREFN
B6
PL_VREFC
A6
PL_NRST
D4
PL_TST
E3
PL_LDO_ENABLE
E4
MPL485A-I/AJA
U1D
NRST
ADVREF
PA[0..31]
PB[0..14]
PL_TST
PL_EMIT
PL_TXRX0
PL_TXRX1
PL_VZC
PL_AGC
PL_VIN
PA0
PA1
PA2
PA3
PA4
PA5
PA7
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA8
PA16
PA19
PA20
PA23
PB0
PB1
PB3
PB4
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB14
PB5
PA6
PA17
PA18
PA31
PB2
PL_LDO_EN
PL_XIN
PL_XOUT
AGND
10000pF
C1
0.022uF
C4
0.022uF
C2
PA[0..31]
PB[0..14]
NRST
DUSB_N
DUSB_P
PL_NRST
PL_CD
PL_EXTIN
PL_NPCS0
PL_SPCK
PL_MOSI
PL_MISO
VDDIO
H5
VDDIO
A4
VDDIO
B4
VDDIN_AN
A5
VDDIN_AN
B8
GND
A1
VDDIO
B10
PL_VDDCORE
B11
VDDPLL
C1
VDDPLL
C2
PL_VDDCORE
D1
VDDIN
E1
VDDIO
E9
VDDIO
E11
VDDIO
D9
VDDIO
E10
GND
A11
GND
C4
GND
C5
GND
C7
GND
C8
GND
C9
GND
D5
GND
D6
GND
D7
GND
D8
GND
H6
GND
H7
GND
J6
GND
L1
GND
L11
GND
B3
GND
C3
AGND
B5
AGND
C6
AGND
A8
VDDIO
J5
VDDIO
K5
MCU_VDDCORE
L2
MCU_VDDCORE
L10
VDDOUT
L7
VDDUSB
J7
MPL485A-I/AJA
U1E
GND
3V3
MCU_VDDCORE
AGND
3V3A
PL_VDDCORE_DEC
VDDPLL
TP2
TP1
PL_CD
PL_EXTIN
PL_MISO
PL_MOSI
PL_SPCK
PL_NPCS0
PL_NRST
PL_TST
PL_LDO_EN
MCU
PLC
POWER PL485
PL_VDDCORE
3V3
10000pF
C3
The following figure shows the recommended connection in the PCB between balls of the PL485 to connect SAMG55
and PL360 internal blocks and the functionalities of GPIO connections.
Figure 3-5. PL485: SAMG55-PL360 Ball Connections at PCB Level
PL485 Ballout
PL360 Signal
D4
PL_NRST
E3
PL_TST
E4
PL_LDO_ENABLE
E5
PL_PA0
E6
PL_PA3
E7
PL_PA8/MOSI
E8
PL_PA9/MISO
G4
PL_PA7/SPCK
G6
PL_PA6/NPCS0
SAMG55 Signal
PL485 Ballout
PA25
F3
PB15
F2
PB13
F4
PA24
F5
PA26
F6
PA28
F7
PA27
F8
PA29
G5
PA30
G7
summarize the functionality of each input/output line of the PL485-EK board.
Table 3-14. Pinout of PL485 PortA in PL485-EK Board
I/O LINE
Function
I/O LINE
Function
PA0/I2SCK0/TIOA0
I2SCK0 / PWM+ (XPLAIN)
PA16/NPCS02
SPI2_NCPS0 (XPLAIN)
PA1/I2SWS0/TIOB0
I2SWS0 / PWM- (XPLAIN)
PA17/AD0
AD0 (mikroBUS)
PA2/I2SDI0/WKUP
I2SDI0 / IRQ (XPLAIN)
PA18/AD1
AD1 (XPLAIN)
PA3/I2SDO0/TWD
I2SDO0 / I2C_SDA
(XPLAIN)
PA19/AD2
UserLed1 / AD2 (XPLAIN)
PA4/I2SMCK0/TWCK3
I2SMCK0 / I2C_SCL
(XPLAIN)
PA20/AD3
AD3 (Voltage Monitor)
PA5/MISO2
SPI2_MISO (XPLAIN)
PA21/DM
DUSB_N (USB Device Diff
Negative)
PL485-EK
PL485-EK Board
©
2020 Microchip Technology Inc.
User Guide
DS50002954B-page 13
