Microchip Technology PIC16F716, Datasheet

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2003 Microchip Technology Inc.
Preliminary
DS41206A-page 15
PIC16F716
2.2.2.5 PIR1 Register
This register contains the individual flag bits for the
peripheral interrupts.
REGISTER 2-5: PIR1 REGISTER (ADDRESS: 0Ch)
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— ADIF — — — CCP1IF TMR2IF TMR1IF
bit 7 bit 0
bit 7 Unimplemented: Read as ‘
0
’
bit 6 ADIF: A/D Converter Interrupt Flag bit
1
= An A/D conversion completed (must be cleared in software)
0
= The A/D conversion is not complete
bit 5-3 Unimplemented: Read as ‘
0
’
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1
= A TMR1 register capture occurred (must be cleared in software)
0
= No TMR1 register capture occurred
Compare Mode
1
= A TMR1 register compare match occurred (must be cleared in software)
0
= No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1
= TMR2 to PR2 match occurred (must be cleared in software)
0
= No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1
= TMR1 register overflowed (must be cleared in software)
0
= TMR1 register did not overflow
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘
0
’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown