MCP401XEV EVALUATION BOARD
USER’S GUIDE
©
2010 Microchip Technology Inc.
DS51888A-page 31
Appendix A. Schematic and Layouts
A.1
INTRODUCTION
This appendix contains the schematics and layouts for the MCP401XEV Evaluation
Board. Diagrams included in this appendix:
• Board - Top Trace, Silk and Pads
• Board - Layer 2 Ground Plane
• Board - Bottom Silk, Trace and Pads
A.2
SCHEMATICS AND PCB LAYOUT
Board - Schematic shows the schematic of the MCP401XEV Evaluation Board. The
layer order is shown in Figure A-1.
FIGURE A-1:
Layer Order.
Top Layer
Ground Layer
Power Layer
Bottom Layer
Summary of Contents for MCP401XEV
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