The baseboard includes numerous peripherals. Many of these are connected to the GPIO block so that the I/O pins
can be configured to carry out many alternative functions. This provides great flexibility to select a function
multiplexing scheme for the pins that satisfy the interface need for a particular application.
Note that most pins are configured as GPIO inputs, with a 100 KOhm pull-up resistor, after reset.
3.7.1
Tamper Interface
The ATSAMA5D27-WLSOM1-EK1 features seven tamper pins for static or dynamic intrusion detection and two
analog pins for comparison.
For a description of intrusion detection, refer to the SAMA5D2 data sheet, chapter “Security Module (SECUMOD)”.
Figure 3-32. Tamper Interface Schematic
1
2
3
4
5
6
7
8
9
10
FTS-105-01-L-DV
J22
330R
R108
330R
R109
330R
R110
330R
R111
330R
R127
330R
R128
0R
R112
0R
R129
0R
R130
COMP_N
COMP_P
PIOBU2
PIOBU4
PIOBU6
PIOBU7
PIOBU3
PIOBU5
PIOBU1
Figure 3-33. Tamper Connector J22 Location
The table below describes the pin assignment of Tamper connector J22.
ATSAMA5D27-WLSOM1-EK1
Baseboard Components
©
2019 Microchip Technology Inc.
User Guide
DS50002931A-page 35
