• MEMS Oscillators for Clock Generation
• 40.8 x 40.8 mm Module, Pitch 0.8mm, Solderable Manually for Prototyping
• 94 I/Os
• Up to 7 Tamper Pins
• One USB Device, one USB Host and one HSIC Interface
• Shutdown and Reset Control Pins
• Operational Specifications:
– Main operating voltage: 3.0V to 5.5V ± 5%
– Temperature range: 0°C to +70°C
– Integrated oscillators, internal voltage regulators
– Multiple interfaces and I/Os for easy application development
3.4.2
Power Supply Topology
3.4.2.1
Input Power
The ATSAMA5D27-WLSOM1-EK1 power source can come through a USB connector (J10) connected to a PC. This
USB power source is sufficient to supply the board in most applications.
Important:
In case of an external device connected through the USB-B port, it is recommended to use
the 5V power supply input with an AC/DC wall adapter for the entire system rather than a PC or a USB
hub, which are limited to 500 mA typical.
Jumper J16 is used to perform VDD_MAIN current measurements on the baseboard.
The following figure is a schematic of the power source.
Figure 3-4. VDD_MAIN Input Powering
VDD_MAIN
JP3
1
2
HDR-2.54 Male 1x2
J16
10uF
10V
0603
C12
GND
10000pF
50V
0402
C10
GND
VBUS_USBA
120R
BLM18PG121SN1D
FB4
100uF
10V
1210
C24
22uF
10V
1206
C25
0.1uF
10V
0402
C26
GND
3.4.2.2
Power Supply Requirements and Restrictions
Detailed information on the device power supplies is provided in tables “SAMA5D2 Power Supplies” and “Power
Supply Connections” in the SAMA5D2 Series datasheet.
3.4.2.3
Power-up and Power-down Considerations
Power-up and power-down considerations are described in section “Power Considerations” of the SAMA5D2 Series
datasheet.
Note:
The power-up and power-down sequences provided in the SAMA5D2 Series datasheet must be respected for
reliable operation of the device. These are respected by the on-board MCP16502.
3.4.2.3.1 LPDDR2 Power-Off Sequence
The LPDDR2 power-off sequence must be controlled by software to preserve the LPDDR2 device.
In this sequence, the CKE signal should be low during the full period the power rails are powering down.
The power failure can be controlled by the embedded Voltage Supervisor (MIC842) and handled at system level (IRQ
on PD31). The LPDDR2 power-off sequence is applied using the bit LPDDR2_LPDDR3_PWOFF in the MPDDRC
Low-Power register (MPDDRC_LPR).
ATSAMA5D27-WLSOM1-EK1
Baseboard Components
©
2019 Microchip Technology Inc.
User Guide
DS50002931A-page 10
