Micro Crystal
Ultra Small Real-Time Clock Module with I
2
C-Bus Interface
RV-8263-C7
January 2019
42/61
Rev. 1.0
SLAVE ADDRESS
5.6.
On the I
2
C-bus the 7-bit slave address 1010001b is reserved for the RV-8263-C7. The entire I
2
C-bus slave address
byte is shown in the following table.
Slave address
W
R/
Transfer data
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
0
0
1
1 ( R )
A3h (read)
0 ( W )
A2h (write)
After a START condition, the I
2
C slave address has to be sent to the RV-8263-C7 device. The
W
R/
bit defines the
direction of the following single or multiple byte data transfer. The 7-bit address is transmitted MSB first. If this
address is 1010001b, the RV-8263-C7 is selected, the eighth bit indicates a read (
W
R/
= 1) or a write (
W
R/
= 0)
operation (results in A3h or A2h) and the RV-8263-C7 supplies the ACK. The RV-8263-C7 ignores all other
address values and does not respond with an ACK.
In the write operation, a data transfer is terminated by sending either the STOP condition or the START condition of
the next data transfer.
WRITE OPERATION
5.7.
Master transmits to Slave-Receiver at specified address. The Register Address is an 8-bit value that defines which
register is to be accessed next. After writing one byte, the Register Address is automatically incremented by 1.
Master writes to slave RV-8263-C7 at specific address:
1) Master sends out the START condition.
2) Master sends out Slave Address, A2h for the RV-8263-C7; the
W
R/
bit is a 0 indicating a write operation.
3) Acknowledgement from RV-8263-C7.
4) Master sends out the Register Address to RV-8263-C7.
5) Acknowledgement from RV-8263-C7.
6) Master sends out the Data to write to the specified address in step 4).
7) Acknowledgement from RV-8263-C7.
8) Steps 6) and 7) can be repeated if necessary.
The address is automatically incremented in the RV-8263-C7.
9) Master sends out the STOP Condition.
S
0
P
A
A
A
REGISTER ADDRESS
SLAVE ADDRESS
DATA
Acknowledge from RV-8263-C7
R
/
W
A
DATA
2
3
4
5
6
1
7
8
9
