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Micro crystal RV-8263-C7, Applications Manual

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Micro Crystal 

 

Ultra Small Real-Time Clock Module with I

2

C-Bus Interface 

RV-8263-C7

 

 

 

January 2019 

26/61 

Rev. 1.0

 

 ALARM FUNCTION 

4.6.

By clearing the alarm enable bit (AE_x) of one or more of the alarm registers, the corresponding alarm condition(s) 
are active. When an alarm occurs, AF is set logic 1. The asserted AF can be used to generate an interrupt (

INT

̅̅̅̅̅

). 

The AF is cleared by command. 
 
The  registers  at  addresses  0Bh  through  0Fh  contain  alarm  information.  When  one  or  more  of  these  registers  is 
loaded with second, minute, hour, date or weekday, and its corresponding AE_x is logic 0, then that information is 
compared  with  the  current  second, minute,  hour,  date,  and  weekday. When  all  enabled  comparisons  first  match, 
the Alarm Flag (AF in CONTROL REGISTERS, 01h 

– Control2) is set logic 1. 

 
Alarm function block diagram: 

 

SECOND ALARM

SECOND TIME

=

MINUTE ALARM

MINUTE TIME

=

HOUR ALARM

HOUR TIME

=

DATE ALARM

DATE TIME

=

WEEKDAY ALARM

WEEKDAY TIME

=

check now signal

ALARM

CONTROL

1
0

AE_S

1
0

AE_M

1
0

AE_H

1
0

AE_D

1
0

AE_W

ALARM FLAG

AF

SET

CLEAR

(1)

from interface:

clear AF

to interface:
read AF

INT

0
1

AIE

 

 

(1) 

Only when all enabled alarm settings are matching. 
It is only on increment to a matched case that the Alarm Flag is set. 

 

 
 

 ALARM INTERRUPT 

4.6.1.

The  generation  of  interrupts  from  the  alarm  function  is  controlled  via  bit  AIE.  If  bit  AIE  is  enabled,  the 

INT

̅̅̅̅̅

  pin 

follows the condition of bit AF. AF remains set until cleared by command. Once AF has been cleared, it will only be 
set again when the time increments to match the alarm condition once more. Alarm registers which have their AE_x 
bit at logic 1 are ignored. 
 
 
 

 

Summary of Contents for RV-8263-C7

Page 1: ...RV 8263 C7 Application Manual January 2019 1 61 Rev 1 0 Application Manual RV 8263 C7 Ultra Small Real Time Clock Module with I2 C Bus Interface ...

Page 2: ...FUNCTIONAL DESCRIPTION 22 POWER ON RESET POR 22 4 1 SOFTWARE RESET 22 4 2 OSCILLATOR STOP FLAG 23 4 3 SETTING AND READING THE TIME 24 4 4 INTERRUPT OUTPUT 25 4 5 ALARM FUNCTION 26 4 6 ALARM INTERRUPT 26 4 6 1 COUNTDOWN TIMER FUNCTION 27 4 7 TIMER FLAG TF 27 4 7 1 TIMER INTERRUPT MODE TI_TP 27 4 7 2 PULSE GENERATOR 2 27 4 7 3 USE OF THE COUNTDOWN TIMER 28 4 7 4 MINUTE AND HALF MINUTE INTERRUPT FUNC...

Page 3: ...ACTERISTICS 48 6 3 1 I 2 C BUS CHARACTERISTICS 49 6 4 7 APPLICATION INFORMATION 50 OPERATING RV 8263 C7 50 7 1 OPERATING RV 8263 C7 WITH BACKUP CAPACITOR 51 7 2 8 PACKAGE 52 DIMENSIONS AND SOLDER PAD LAYOUT 52 8 1 RECOMMENDED THERMAL RELIEF 52 8 1 1 MARKING AND PIN 1 INDEX 53 8 2 9 MATERIAL COMPOSITION DECLARATION ENVIRONMENTAL INFORMATION 54 HOMOGENOUS MATERIAL COMPOSITION DECLARATION 54 9 1 MATE...

Page 4: ... kHz and 1 Hz with enable disable function CLKOE I 2 C bus interface up to 400 kHz Wide operating voltage range 0 9 V to 5 5 V Wide interface operating voltage 1 8 to 5 5 V Very low current consumption 190 nA VDD 3 0 V TA 25 C Operating temperature range 40 to 85 C Ultra small and compact C7 package size RoHS compliant and 100 lead free 3 2 x 1 5 x 0 8 mm Automotive qualification according to AEC ...

Page 5: ...and Tags Handsets Automotive M2M Navigation Tracking Systems Dashboard Tachometers Engine Controller Car Audio Entertainment Systems Metering E Meter Heating Counter Smart Meters PV Converter Outdoor ATM POS systems Surveillance Safety systems Ticketing Systems Medical Glucose Meter Health Monitoring Systems Safety DSLR Security Camera Systems Door Lock Access Control Consumer Gambling Machines TV...

Page 6: ...M CONTROL LOGIC INPUT OUTPUT CONTROL RESET CLKOUT VSS VDD POWER CONTROL XTAL OSC DIVIDER FREQUENCY OFFSET COMPENSATION CLKOE Seconds Alarm Year Month Weekday Date Hours RAM Offset Control2 Control1 Date Alarm Hours Alarm Minutes Alarm Seconds 5 2 6 4 INT Minutes Timer Mode Timer Value Weekday Alarm 11 00 SCL SDA I2 C BUS INTERFACE 3 7 ...

Page 7: ...e LOW requires pull up resistor Used to output alarm minute half minute countdown timer and compensation Interrupt signals VDD 5 Power Supply Voltage CLKOUT 6 Clock Output push pull controlled by CLKOE If CLKOE is HIGH VDD the CLKOUT pin drives the square wave of 32 768 kHz 16 384 kHz 8 192 kHz 4 096 kHz 2 048 kHz 1 024 kHz or 1 Hz Default value is 32 768 kHz When CLKOE is tied to Ground the CLKOU...

Page 8: ... 03h 0Fh 10h 11h Address wrap around auto increment All registers see REGISTER OVERVIEW are designed as addressable 8 bit parallel registers although not all bits are implemented The first two registers memory address 00h and 01h are used as control and status register The register at address 02h is an Offset register allowing the compensation of time deviation The register at address 03h is a fre...

Page 9: ...Micro Crystal Ultra Small Real Time Clock Module with I 2 C Bus Interface RV 8263 C7 January 2019 9 61 Rev 1 0 DEVICE PROTECTION DIAGRAM 2 4 VDD VSS SDA NC CLKOE CLKOUT SCL INT 2 1 3 4 5 6 7 8 ...

Page 10: ...ry condition is prevented REGISTER OVERVIEW 3 1 After reset all registers are set according to Table in section REGISTER RESET VALUES SUMMARY Address Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00h Control1 TEST SR STOP SR CIE 12_24 CAP 01h Control2 AIE AF MI HMI TF FD 02h Offset MODE OFFSET 03h RAM RAM data 04h Seconds OS 40 20 10 8 4 2 1 05h Minutes X 40 20 10 8 4 2 1 06h Hours 24 h...

Page 11: ...t this bit always returns a 0 when read For a software reset 01011000 58h must be sent to register Control1 5 STOP STOP bit see STOP BIT FUNCTION 0 RTC clock runs 1 RTC clock is stopped the upper part of the RTC divider chain flip flops prescaler F2 to F14 are asynchronously set logic 0 The CLKOUT frequencies 32 768 kHz 16 384 kHz and 8 192 kHz are still available 4 3 SR Software Reset see SOFTWAR...

Page 12: ...ive Write Alarm Flag remains unchanged 5 MI Minute Interrupt Enable see MINUTE AND HALF MINUTE INTERRUPT FUNCTION and TIMER FLAG TF 0 Disabled 1 Enabled 4 HMI Half Minute Interrupt Enable see MINUTE AND HALF MINUTE INTERRUPT FUNCTION and TIMER FLAG TF 0 Disabled 1 Enabled 3 TF Timer Flag see COUNTDOWN TIMER FUNCTION INTERRUPT OUTPUT and TIMER FLAG TF 0 No timer interrupt generated 1 Flag set when ...

Page 13: ...ed on a nominal 32 768 kHz clock The offset value is coded in two s complement giving a range of 63 LSB to 64 LSB see FREQUENCY OFFSET COMPENSATION OFFSET OFFSET compensation value in decimal Compensation pulses in steps CLKOUT frequency offset in ppm 1 Normal Mode MODE 0 Fast Mode MODE 1 0111111 63 63 273 420 256 347 0111110 62 62 269 080 252 278 0000001 1 1 4 340 4 069 0000000 0 0 0 0 1111111 12...

Page 14: ...Bit 2 Bit 1 Bit 0 05h Minutes X 40 20 10 8 4 2 1 Reset 0 0 0 0 0 0 0 0 Bit Symbol Value Description 7 X 0 Unused 6 0 Minutes 00 to 59 Holds the count of minutes coded in BCD format 06h Hours This register holds the count of hours in two binary coded decimal BCD digits If the 12_24 bit is cleared default see CONTROL REGISTERS 00h Control1 the values will be from 0 to 23 If the 12_24 bit is set the ...

Page 15: ...sed 5 0 Date 01 to 31 Holds the current date of the month coded in BCD format Default value 01 08h Weekday This register holds the current day of the week Each value represents one weekday that is assigned by the user Values will range from 0 to 6 Address Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 08h Weekday X X X X X 4 2 1 Reset 0 0 0 0 0 1 1 0 Bit Symbol Value Description 7 3 X 0 ...

Page 16: ...Month Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 January Default value 0 0 0 0 0 0 0 1 February 0 0 0 1 0 March 0 0 0 1 1 April 0 0 1 0 0 May 0 0 1 0 1 June 0 0 1 1 0 July 0 0 1 1 1 August 0 1 0 0 0 September 0 1 0 0 1 October 1 0 0 0 0 November 1 0 0 0 1 December 1 0 0 1 0 0Ah Year This register holds the current year in two binary coded decimal BCD digits Values will range from 00 to 99 Lea...

Page 17: ...7 AE_S Seconds Alarm Enable bit see ALARM FUNCTION 0 Enabled 1 Disabled Default value 6 0 Seconds Alarm 00 to 59 Holds the alarm value for seconds coded in BCD format 0Ch Minutes Alarm This register holds the Minutes Alarm Enable bit AE_M and the alarm value for minutes in two binary coded decimal BCD digits Values will range from 00 to 59 Address Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...

Page 18: ...t 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Dh Hours Alarm 24 hour mode default value AE_H X 20 10 8 4 2 1 Hours Alarm 12 hour mode AMPM 10 8 4 2 1 Reset 1 0 0 0 0 0 0 0 Hours Alarm 24 hour mode 12_24 0 default value Bit Symbol Value Description 7 AE_H Hours Alarm Enable bit see ALARM FUNCTION 0 Enabled 1 Disabled Default value 6 X 0 Unused 5 0 Hours Alarm 24 hour mode default value 00 to 23 Holds the alar...

Page 19: ...le bit see ALARM FUNCTION 0 Enabled 1 Disabled Default value 6 X 0 Unused 5 0 Date Alarm 01 to 31 Holds the alarm value for the date coded in BCD format 0Fh Weekday Alarm This register holds the Weekday Alarm Enable bit AE_W and the alarm value for the weekday in two binary coded decimal BCD digits Values will range from 0 to 6 Address Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Fh W...

Page 20: ... 3 Bit 2 Bit 1 Bit 0 11h Timer Mode X X X TD TE TIE TI_TP Reset 0 0 0 1 1 0 0 0 Bit Symbol Value Description 7 5 X 0 Unused 4 3 TD Timer Clock Frequency see COUNTDOWN TIMER FUNCTION 1 00 4 096 kHz 01 64 Hz 2 10 1 Hz 2 11 1 60 Hz Default value 2 2 TE Timer Enable 0 Disabled Default value 1 Enabled 1 TIE Timer Interrupt Enable 0 No interrupt generated from timer Default value 1 Interrupt generated f...

Page 21: ...0 0 0 0 07h Date 0 0 0 0 0 0 0 1 08h Weekday 0 0 0 0 0 1 1 0 09h Month 0 0 0 0 0 0 0 1 0Ah Year 0 0 0 0 0 0 0 0 0Bh Seconds Alarm 1 0 0 0 0 0 0 0 0Ch Minutes Alarm 1 0 0 0 0 0 0 0 0Dh Hours Alarm 24h 12h 1 0 0 0 0 0 0 0 0Eh Date Alarm 1 0 0 0 0 0 0 0 0Fh Weekday Alarm 1 0 0 0 0 0 0 0 10h Timer Value 0 0 0 0 0 0 0 0 11h Timer Mode 0 0 0 1 1 0 0 0 RV 8263 C7 resets to Time hh mm ss 00 00 00 Date YY ...

Page 22: ...reset must be initiated with the software reset command after power up i e when power is stable See following section SOFTWARE RESET SOFTWARE RESET 4 2 Beside the POR a reset can also be initiated with the software reset command Software reset command requires a combination of the bits 6 4 and 3 in register Control1 00h set to 1 and all other bits to 0 by sending the bit sequence 01011000 58h see ...

Page 23: ...200 ms to maximal 2 s depending on temperature and supply voltage The flag remains set until cleared by command see following Figure If the flag cannot be cleared then the oscillator is not running This method can be used to monitor the oscillator and to determine if the supply voltage has reduced to the point where oscillation fails OS flag VDD oscillation OS flag OS 1 and flag cannot be cleared ...

Page 24: ...erminated within 1 second t 1 s the time circuit is de frozen immediately and any pending request to increment the time counters that occurred during the read write access is correctly applied Maximal one 1 Hz tick can be handled When the read write access last longer than 1 second the time circuit is de frozen automatically after 1 second in order not to miss 1 Hz ticks and the lost 1 Hz ticks ca...

Page 25: ...ION INTERRUPT FUNCTION Interrupt scheme SECONDS COUNTER MINUTES COUNTER HMI MI ALARM FLAG AF SET CLEAR SET CLEAR from interface clear TF PULSE GENERATOR 1 TRIGGER CLEAR PULSE GENERATOR 3 TRIGGER set alarm flag AF from interface clear AF offset circuit add subtract pulse from interface clear CIE CLEAR to interface read AF TI_TP 0 1 INT COUNTDOWN COUNTER TE TIMER FLAG TF SET CLEAR PULSE GENERATOR 2 ...

Page 26: ...rst match the Alarm Flag AF in CONTROL REGISTERS 01h Control2 is set logic 1 Alarm function block diagram SECOND ALARM SECOND TIME MINUTE ALARM MINUTE TIME HOUR ALARM HOUR TIME DATE ALARM DATE TIME WEEKDAY ALARM WEEKDAY TIME check now signal ALARM CONTROL 1 0 AE_S 1 0 AE_M 1 0 AE_H 1 0 AE_D 1 0 AE_W ALARM FLAG AF SET CLEAR 1 from interface clear AF to interface read AF INT 0 1 AIE 1 Only when all ...

Page 27: ...he next coming interrupt no INT is generated When Interrupt is in Timer Pulse Mode TI_TP 1 the Countdown Timer runs in a repetitive loop and keeps generating periodic interrupts an INT pulse is generated independent of the status of the Timer Flag TF TF stays set until it is cleared TF does not affect INT PULSE GENERATOR 2 4 7 3 When the Timer Pulse Mode is activated TI_TP 1 the Pulse Generator 2 ...

Page 28: ...ppm at 25 C The timer counts down from the software loaded 8 bit binary Timer Value in register 10h Timer Values from 1 to 255 are valid Loading the counter with 0 stops the timer When the counter decrements from 1 the Timer Flag bit TF in register Control2 is set and the counter automatically re loads and starts the next timer period General countdown timer behavior Timer Value Timer Clock Countd...

Page 29: ...ith 0 stops the timer At the end of every countdown the timer sets the countdown Timer Flag bit TF in register Control2 Bit TF can only be cleared by command The asserted bit TF can be used to generate an interrupt at pin INT The interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of bit TF Bit TI_TP is used to control ...

Page 30: ...ly from one another However a Minute Interrupt enabled on top of a Half Minute Interrupt is not distinguishable INT example for MI seconds counter minutes counter INT when MI enabled TF when MI enabled 58 59 59 00 00 01 11 12 In this example the TF flag is not cleared after an interrupt and the pin INT is set to Pulse Mode TI_TP bit 1 Effect of bits MI and HMI on INT generation Minute Interrupt bi...

Page 31: ... on a nominal 32 768 kHz clock The offset value is coded in two s complement giving a range of 63 LSB to 64 LSB OFFSET OFFSET compensation value in decimal Compensation pulses in steps CLKOUT offset value in ppm 1 Normal Mode MODE 0 Fast Mode MODE 1 0111111 63 63 273 420 256 347 0111110 62 62 269 080 252 278 0000001 1 1 4 340 4 069 0000000 0 0 0 0 1111111 127 1 4 340 4 069 1111110 126 2 8 680 8 13...

Page 32: ...m fCLKOUT 32768 32768 1 000 000 Compute the CLKOUT offset value in compensation pulses MODE 0 Normal Mode Pulses Offset ppm 4 34 ppm MODE 1 Fast Mode Pulses Offset ppm 4 069 ppm Compute the OFFSET compensation value If Pulses 63 or 64 fCLKOUT is out of range to be corrected Else if 0 Pulses 63 set OFFSET Pulses Else if 64 Pulses 1 set OFFSET Pulses 128 32768 48 Hz 14 648 ppm 3 375 à 3 compensaton ...

Page 33: ...et ppm Reachable accuracy zone With the offset compensation the accuracy of 2 17 ppm 0 5 offset per LSB can be reached see CONTROL REGISTERS 02h Offset Register 1 ppm corresponds to a time deviation of 0 0864 seconds per day 1 MODE 0 Deviation after compensation Offset ppm compensation pulses 4 34 ppm 14 648 ppm 3 4 34 ppm 1 628 ppm 2 MODE 1 Deviation after compensation Offset ppm compensation pul...

Page 34: ... been compensated Compensation pulses when MODE 0 Compensation pulses in steps Update every nth hour Minute Compensation pulses on INT per minute 1 1 or 1 2 00 1 2 or 2 2 00 and 01 1 3 or 3 2 00 01 and 02 1 59 or 59 2 00 to 58 1 60 or 60 2 00 to 59 1 61 or 61 2 00 to 59 1 2nd and next hour 00 1 62 or 62 2 00 to 59 1 2nd and next hour 00 and 01 1 63 or 63 2 00 to 59 1 2nd and next hour 00 01 and 02...

Page 35: ...nsation pulses on INT per second 1 1 or 1 4 00 1 2 or 2 4 00 and 01 1 3 or 3 4 00 01 and 02 1 59 or 59 4 00 to 58 1 60 or 60 4 00 to 59 1 61 or 61 4 00 to 58 1 4 59 2 62 or 62 4 00 to 58 1 4 59 3 63 or 63 4 00 to 58 1 4 59 4 64 4 00 to 58 1 4 59 5 1 When MODE 1 the compensation pulses on pin INT are 977 µs wide For multiple pulses they are repeated at an interval of 1 953 ms In MODE 1 CLKOUT or Ti...

Page 36: ...ed the CLKOUT is LOW The duty cycle of the selected clock is not controlled However due to the nature of the clock generation all are 50 50 except the 32 768 kHz frequency The STOP bit function can also affect the CLKOUT signal depending on the selected frequency When the STOP bit is set logic 1 the CLKOUT pin generates a continuous LOW for those frequencies that can be stopped for more details se...

Page 37: ...0100 12 45 12 Prescaler counting normally STOP bit is activated by user F0F1 are not reset and values cannot be predicted externally 1 XX 0 0000 0000 0000 12 45 12 Prescaler is reset time circuits are frozen New time is set by user 1 XX 0 0000 0000 0000 08 00 00 Prescaler is reset time circuits are frozen STOP bit is released by user 0 XX 0 0000 0000 0000 0 507813 to 0 507935 s 1 000000 s 08 00 00...

Page 38: ...Rev 1 0 STOP bit release timing 8192 Hz stop released 0 µs to 122 µs The first increment of the time circuits is between 0 507813 s and 0 507935 s after STOP bit is released The uncertainty is caused by the prescaler bits F0 and F1 not being reset see Table above and the unknown state of the 32 kHz clock ...

Page 39: ...remain HIGH when the bus is not busy A HIGH to LOW transition of the data line while the clock is HIGH is defined as the START condition S A LOW to HIGH transition of the data line while the clock is HIGH is defined as the STOP condition P see Figure below Definition of START and STOP conditions SDA SCL S START condition P STOP condition SDA SCL A START condition which occurs after a previous STAR...

Page 40: ... multiple devices can be connected with the I 2 C bus all I 2 C bus devices have a fixed and unique device number built in to allow individual addressing of each device The device that controls the I 2 C bus is the Master the devices which are controlled by the Master are the Slaves A device generating a message is a Transmitter a device receiving a message is the Receiver The RV 8263 C7 acts as a...

Page 41: ...at has been clocked out of the slave transmitter The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse set up and hold times must be taken into consideration A master receiver must signal an end of data to the transmitter by not generating an acknowledge cycle on t...

Page 42: ...nd with an ACK In the write operation a data transfer is terminated by sending either the STOP condition or the START condition of the next data transfer WRITE OPERATION 5 7 Master transmits to Slave Receiver at specified address The Register Address is an 8 bit value that defines which register is to be accessed next After writing one byte the Register Address is automatically incremented by 1 Ma...

Page 43: ...event the Slave Transmitter must leave the data line HIGH to enable the Master to generate a STOP condition 13 Master sends out the STOP condition P A DATA DATA S 0 A S A SLAVE ADDRESS SLAVE ADDRESS 1 R W R W REGISTER ADDRESS A Acknowledge from Master Acknowledge from RV 8263 C7 2 3 4 5 6 1 7 8 9 10 11 12 13 No acknowledge from Master A Repeated START READ OPERATION 5 9 Master reads data from slav...

Page 44: ...I Input voltage 0 5 6 5 V VO Output voltage 0 5 6 5 V II Input current At any input 10 10 mA IO Output current At any output 10 10 mA PTOT Total power dissipation 300 mW VESD Electrostatic discharge Voltage HBM 1 5000 V CDM 2 2000 V ILU Latch up current 3 200 mA TOPR Operating temperature 40 85 C TSTO Storage temperature Stored as bare product 55 125 C TPEAK Maximum reflow condition JEDEC J STD 02...

Page 45: ...GH level output voltage On pin CLKOUT 0 8 VDD VDD V VOL LOW level output voltage On pins SDA INT CLKOUT VSS 0 2 VDD V IOH HIGH level output current Output source current On pin CLKOUT VOH 2 6 V VDD 3 0 V 1 3 mA IOL LOW level output current Output sink current On pins SDA VOL 0 4 V VDD 3 0 V 3 8 5 mA On pins INT VOL 0 4 V VDD 3 0 V 2 6 mA On pin CLKOUT VOL 0 4 V VDD 3 0 V 1 3 mA 1 For reliable osci...

Page 46: ...2 C active Typical IDD with respect to fSCL 40 30 20 10 0 IDD µA 0 100 200 300 400 500 fSCL kHz 2 50 1 TA 25 C CLKOUT disabled 1 VDD 5 5 V 2 VDD 3 0 V Timekeeping mode Typical IDD as a function of temperature 800 600 400 200 0 IDD nA 1 2 50 30 10 10 30 50 70 90 Temperature C CLKOUT disabled 1 VDD 5 5 V 2 VDD 3 0 V ...

Page 47: ...7 61 Rev 1 0 Timekeeping mode Typical IDD with respect to VDD 0 1 2 3 4 5 6 VDD V 300 200 150 100 IDD nA 50 0 250 TA 25 C timer clock frequency 1 60 Hz CLKOUT disabled Oscillator frequency variation with respect to VDD 0 1 2 3 4 5 6 VDD V 10 6 2 2 6 f f ppm 4 0 4 8 10 8 TA 25 C normalized to VDD 3 V ...

Page 48: ... Frequency vs voltage characteristics 1 ppm V Δf fTOPR Frequency vs temperature characteristics TOPR 40 C to 85 C VDD 3 0 V 0 035ppm C 2 TOPR T0 2 10 ppm T0 Turnover temperature 20 30 C Δf f Aging first year max TA 25 C VDD 3 0 V 3 ppm Frequency Offset Compensation Δt t OFFSET value when MODE 0 Min comp step LSB and Max comp range TA 40 C to 85 C 4 34 273 4 277 8 ppm Δt t OFFSET value when MODE 1 ...

Page 49: ...VDD 5 5 V 300 ns tHD STA START condition hold time 0 6 µs tSU STA START condition setup time 0 6 µs tSU DAT SDA setup time 100 ns tHD DAT SDA hold time 0 µs tSU STO STOP condition setup time 0 6 µs tBUF Bus free time before a new transmission 1 3 µs tVD DAT Data valid time 0 0 9 µs tVD ACK Data valid acknowledge time 0 0 9 µs tSP Spike pulse width 0 50 ns Cb Capacitive load for each bus line 400 p...

Page 50: ...tor is recommended close to the device 2 The INT output is an open drain and requires a pull up resistor to VDD 3 CLKOUT offers selectable frequencies from 32 768 kHz to 1 Hz for application use If not used it is recommended to disable CLKOUT for optimized current consumption by setting FD to 111b or by pulling CLKOE LOW When disabled the CLKOUT is LOW Further current minimization can be achieved ...

Page 51: ...harging voltage 5 When using a supercapacitor a resistor is used to limit the inrush current into the supercapacitor at power on E g to comply with the maximum forward current of the schottky diode or When using a battery a resistor is used to limit the maximum current in case of a short circuit 6 Schottky diode This low VF diode less than 0 3 V is needed to not exceed the specified maximum voltag...

Page 52: ...om view Recommended solder pad layout 0 4 3 2 0 4 0 8 2 0 1 5 0 9 0 8 0 9 0 5 0 15 3 2 0 9 0 9 0 5 1 5 3 7 4 2 6 8 0 8 max Metal lid is connected to VSS pin 2 Tolerances unless otherwise specified 0 1mm Drawing RV 8263 C7_Pack drw_20180918 All dimensions in mm typical RECOMMENDED THERMAL RELIEF 8 1 1 When connecting a pad to a copper plane thermal relief is recommended RV C7 Package GOOD P BAD O ...

Page 53: ...ll Real Time Clock Module with I 2 C Bus Interface RV 8263 C7 January 2019 53 61 Rev 1 0 MARKING AND PIN 1 INDEX 8 2 Laser marking RV 8263 C7 Package top view 1 4 5 8 M835A1 8263 Product Date Code Pin 1 Index Part Designation ...

Page 54: ...0 100 Al2O3 1344 28 1 4 Metal Lid Kovar Lid 2 67 95 Fe53Ni29Co18 Fe Ni Co 7439 89 6 7440 02 0 7440 48 4 Metal Lid Kovar Ni plating 4 95 Ni Ni 7440 02 0 Nickel plating Au plating 0 05 Au Au 7440 57 5 Gold plating 5 Seal Solder Preform 0 54 80 Au80 Sn20 Au 7440 57 5 20 Sn 7440 31 5 6 Terminations Internal and external terminals 0 38 80 Mo Mo 7439 98 7 Molybdenum 15 Ni Ni 7440 02 0 Nickel plating 5 A...

Page 55: ... nd nd nd nd nd nd nd 4 Metal Lid Kovar Lid Plating nd nd nd nd nd nd nd nd nd nd nd nd nd nd 5 Seal Solder Preform nd nd nd nd nd nd nd nd nd nd nd nd nd nd 6 Terminations Int ext terminals nd nd nd nd nd nd nd nd nd nd nd nd nd nd 7 Conductive adhesive Silver filled Silicone glue nd nd nd nd nd nd nd nd nd nd nd nd nd nd 8 CMOS IC Silicon Gold bumps nd nd nd nd nd nd nd nd nd nd nd nd nd nd MDL ...

Page 56: ... 60 74 Al2O3 1344 28 1 Gold 2 4 5 6 8 Electrodes Metal Lid Seal Terminations CMOS IC 0 53 4 63 Au Au 7440 57 5 Tin 5 Seal 0 11 0 95 Sn Sn 7440 31 5 Nickel 4 6 Metal Lid Terminations 0 19 1 67 Ni Ni 7440 02 0 Molybdenum 6 Terminations 0 3 2 68 Mo Mo 7439 98 7 Kovar 4 Metal Lid 2 53 22 33 Fe53Ni29Co18 Fe Ni Co 7439 89 6 7440 02 0 7440 48 4 Silver 7a Conductive adhesive 0 079 0 7 Ag Ag 7440 22 4 Silo...

Page 57: ...NGS 9 4 Package Description SON 8 Small Outline Non leaded SON ceramic package with metal lid Parameter Directive Conditions Value Product weight total 11 4 mg Storage temperature Store as bare product 55 to 125 C Moisture sensitivity level MSL IPC JEDEC J STD 020D MSL1 FIT MTBF available on request Terminal finish Ceramic Molybdenum Nickel Gold 5 µm 0 5 µm ...

Page 58: ...e TL to TP Tsmax Ramp down Temperature Profile Symbol Condition Unit Average ramp up rate Tsmax to TP 3 C second max C s Ramp down Rate Tcool 6 C second max C s Time 25 C to Peak Temperature Tto peak 8 minutes max min Preheat Temperature min Tsmin 150 C Temperature max Tsmax 200 C Time Tsmin to Tsmax ts 60 180 sec Soldering above liquidus Temperature liquidus TL 217 C Time above liquidus tL 60 150...

Page 59: ...brations on the PCB that have a fundamental or harmonic frequency close to 32 768 kHz This might cause breakage of crystal blanks due to resonance Router speed should be adjusted to avoid resonant vibration Ultrasonic cleaning Avoid cleaning processes using ultrasonic energy These processes can damage crystals due to mechanical resonance of the crystal blank Overheating rework high temperature exp...

Page 60: ...th 12 mm Tape Leader and Trailer Minimum length 300 mm 2 0 05 4 0 1 3 43 0 05 4 0 1 Ø 1 0 0 0 5 Ø 1 5 0 1 12 5 5 0 05 1 75 0 1 0 254 0 015 1 73 0 05 0 83 0 05 0 061 Cover Tape 0 315 0 05 0 3 0 1 All dimensions are in mm RV 8263 C7_Tape drw_20181002 Direction of feed 8263 8263 Cover Tape Tape Polypropylene 3M Universal Cover Tape UCT Adhesive Type Pressure sensitive Synthetic Polymer Thickness 0 06...

Page 61: ...release Information furnished is believed to be accurate and reliable However Micro Crystal assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use In accordance with our policy of continuous development and improvement Micro Crystal reserves the right to modify specifications menti...

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