Micrel, Inc.
SY87725L Evaluation Board
July 2008
8
M9999-071108-B
or (408) 955-1690
CDR Bypass Mode
Verifies correct operation of the receive DeMux. In this
mode the CDR is bypassed so the serial data coming into
SIN must be clocked in by the serial clock coming into the
RefClk input. In this mode only, the RefCLK will be
155.52MHz or 77.76MHz and must be at the same
rate as the Serial Data In (SIN). For example, if REFCLK
is 155.52MHz, then SIN must be at 155.52Mbps. The 4-
bit parallel data at the output of DOUT0-3 can be verified
with a parallel BERT.
Figure 4. Switch Settings for CDR Bypass Mode
Switch Settings
Function
RCV_DDRSEL = 0
Sets receive CLKOUT frequency
to be the RefClk frequency
divided-by 4. (If RCV_DDRSEL =
1, the CLKOUT frequency will be
the RefClk frequency divided-by
8.)
RCV_CTRL0/1 = 01
RefClk & SIN bypass CDR
(RefClk must be at the clock rate
of SIN data.)
TESTb = 1
Disables factory test mode
(enables normal operation)
Table 5. Required Switch Settings for
CDR Bypass Mode Data Flow
