KSZ9031MNX-EVAL Board User’s Guide
Micrel, Inc.
August 17, 2012
Rev.
1.0
9/23
The following table lists the strapping pin definitions for the KSZ9031MNX-EVAL board jumpers.
Jumper
Pin
Pin Name
Pin Function
JP1
JP2
JP3
JP4
39
41
43
44
MODE3
MODE2
MODE1
MODE0
The MODE[3:0] strap-in pins are latched at power-up /
reset and are defined as follows:
MODE[3:0] Mode
0001 GMII
/
MII
0100 NAND
Tree
0111
Chip Power Down
All other MODE[3:0] settings not listed are reserved and
are not used by the KSZ9031MNX-EVAL.
MODE[3:0] = 0001 is set as the default for the board.
JP11
JP12
JP13
48
17
19
PHYAD2
PHYAD1
PHYAD0
The PHY Address is latched at power-up / reset and is
configurable to any value from 0 to 7.
PHY Address bits [4:3] are always set to ‘00’.
PHYAD[2:0] = 001 is set as the default for the board.
JP10 45
CLK125_EN
CLK125_EN is latched at power-up / reset and is defined
as follows:
Pull-up (1) = Enable 125MHz Clock Output
Pull-down (0) = Disable 125MHz Clock Output
Pin 56 (CLK125_NDO) provides the 125MHz reference
clock output option for use by the MAC.
CLK125_EN = 0 is set as the default for the board.
JP9 56
LED_MODE
LED_MODE is latched at power-up / reset and is defined
as follows:
Pull-up (1) = Single LED Mode
Pull-down (0) = Tri-color Dual LED Mode
LED_MODE = 1 is set as the default for the board.
Table 2. Strapping Pin Definitions for KSZ9031MNX-EVAL Board Jumpers
