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5I25
ANYTHING I/O
MANUAL

Version 1.10

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Summary of Contents for 5i25

Page 1: ...5I25 ANYTHING I O MANUAL Version 1 10...

Page 2: ...This page intentionally not blank...

Page 3: ...ITIONS 4 5I25 I O CONNECTOR PIN OUT 5 JTAG CONNECTOR PIN OUT 7 OPERATION 8 FPGA 8 FPGA PINOUT 8 PCI ACCESS 8 CONFIGURATION 9 EEPROM LAYOUT 9 BITFILE FORMAT 12 NMFLASH 12 MESAFLASH 12 SPI INTERFACE DES...

Page 4: ...of Contents SUPPLIED CONFIGURATIONS 17 HOSTMOT2 17 7I76X2 17 7I76_7I74 17 G540X2 17 7I77X2 17 7I77_7I76 17 7I77_7I74 18 7I74X2 18 7I78X2 18 PROB_RFX2 18 PIN FILES 18 REFERENCE INFORMATION 19 SPECIFICA...

Page 5: ...dware step generation to MHz rates encoder counting PWM digital I O analog I O and Smart Serial remote I O Configurations are available that are compatible with common breakout cards and multi axis st...

Page 6: ...pt 5V power on DB25 pins 22 through 25 When the option is disabled DB25 pins 22 through 25 are grounded W1 P2 POWER W2 P3 POWER UP UP BREAKOUT POWER ENABLED DOWN DOWN BREAKOUT POWER DISABLED DEFAULT 5...

Page 7: ...d be placed in the UP position To disable the internal pull ups W4 should be in the DOWN position PCI BUS ISOLATION The 5I25 uses bus switches to provide 5V tolerance on the PCI bus These bus switches...

Page 8: ...5I25 4 CONNECTORS CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS...

Page 9: ...I25IO PIN file on the 5I25 distribution disk 5I25 IO connector pinouts are as follows P3 BACK PANEL DB25F CONNECTOR PINOUT DB25 PIN FUNCTION DB25 PIN FUNCTION 1 IO0 14 IO1 2 IO2 15 IO3 3 IO4 16 IO5 4...

Page 10: ...GND 13 IO27 14 GND 15 IO28 16 GND 17 IO29 18 GND or 5V 19 IO30 20 GND or 5V 21 IO31 22 GND or 5V 23 IO32 24 GND or 5V 25 IO33 26 GND or 5V Note 26 pin header P2 will match standard parallel port pin o...

Page 11: ...configuration has been corrupted In case of corrupted EEPROM contents the EEPROM can be re programmed using Xilinx s Impact tool For reprogramming the card can be powered in a standard PCI slot or if...

Page 12: ...ource directory of the 5i25 zip file PCI ACCESS The 5I25 normally uses 5I25 specific HostMot2 firmware which currently has a simple target only PCI core with a single Base Address Register BAR 0 Card...

Page 13: ...PROM LAYOUT The EEPROM used on the 5I25 for configuration storage is the M25P80 or M25P16 The M25P80 is a 8 M bit 1 M byte EEPROM with 16x 64K byte sectors The M25P16 is a 16 Mbit 2 M byte EEPROM with...

Page 14: ...CK CONFIGURATION BLOCK 1 0x30000 FALLBACK CONFIGURATION BLOCK 2 0x40000 FALLBACK CONFIGURATION BLOCK 3 0x50000 FALLBACK CONFIGURATION BLOCK 4 0x60000 FALLBACK CONFIGURATION BLOCK 5 0x70000 RESERVED 0x...

Page 15: ...1 0x120000 USER CONFIGURATION BLOCK 2 0x130000 USER CONFIGURATION BLOCK 3 0x140000 USER CONFIGURATION BLOCK 4 0x150000 USER CONFIGURATION BLOCK 5 0x160000 UNUSED FREE 0x170000 UNUSED FREE 0x180000 UNU...

Page 16: ...FPGAFILE BIT to the user area of the EEPROM NMFLASH FPGAFILE BIT V Verifies the user EEPROM configuration against the bit file FPGAFILE BIT NMFLASH FALLBACK BIT FallBack Writes the fallback EEPROM con...

Page 17: ...This hardware is built into all Mesa 5I25 configurations This information is only needed if you are writing your own programming utility DATA REGISTER at offset 0x74 from 5I25 base address D7 D6 D5 D...

Page 18: ...free when both user and fallback configurations are installed It is suggested that only the last two blocks 0xE0000 and 0xF0000 in the user area be used for FPGA application EEPROM storage FALLBACK IN...

Page 19: ...ve programmable I O levels for interfacing with different logic families The 5I25 does not support use of the I O standards that require input reference voltages All standard Mesa configurations use L...

Page 20: ...ion in 6 and 10 foot lengths BREAKOUT POWER OPTION When used with Mesa breakout daughter cards the 5I25 can supply up to 1A of 5V power to each of the daughter cards This option is disabled by default...

Page 21: ...imer and GPIO 7I76_7I74 7I76_7I74 is a configuration for one 7I76 five axis step dir daughtercards on P3 and one 7I74 eight channel RS 422 interface on P2 The 7I74 is configured with eight Smart Seria...

Page 22: ...re step generators two PWM generators two encoder inputs two Smart Serial interfaces a watchdog timer and GPIO 7I76_7I78 7I76_7I78 is a configuration designed to work with the 7I76 five axis step dir...

Page 23: ...PLY 3 0V 3 6V PCI supplied 3 3V 5V POWER SUPPLY 4 5V 5 5V PCI supplied 5V 3 3V POWER CONSUMPTION 400 mA Depends on FPGA Configuration MAX 5V CURRENT TO I O CONNS 1000 mA Each PTC Limit TEMPERATURE RAN...

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