MESA Electronic 4I24M Series, Manual

Page: 12 / 19

OPERATION
PORT MAPPING
The 4I24M has three 82C55 chips. Each 82C55 chip occupies four contiguous locations in I/O
space, for a total of twelve I/O locations, but the 4I24M decoding scheme actually uses sixteen I/O
locations per 4I24M card, with the last four locations per card not used.
In the following table and I/O connector pinout tables the letters A, B, and C refer to individual
ports on a 8255 chip (the standard 8255 port names), while the numeric suffix 0,1, or 2 refers to the
specific chip.
The 82C55 ports are addressed as follows:
ADDRESS PORT CONNECTOR
BASE +0 A0 P3
BASE +1 B0 P3
BASE+2 C0 P3
BASE+3 Control 0
BASE+4 A1 P1
BASE +5 B1 P1
BASE+6 C1 P1
BASE+7 Control 1
BASE+8 A2 P2
BASE +9 B2 P2
BASE+A C2 P2
BASE+B Control 2
BASE+C XXX
BASE +D XXX
BASE+E XXX
BASE+F XXX
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4I24M USER'S MANUAL