DMU380ZA Series
User’s Manual
________________________________________________________________________
Doc# 7430-3810 Rev. 02
Page 40
Configuration Registers
5.7
5.7.1
Self-Test/Data-Ready
Self-test and data-ready registers are combined into a single 16-bit register at memory
location 0x34; individual bits are assigned according to Table 25.
Table 25 Self-Test/Data-Ready Register
(Base Address: 0x34), Read/Write
Bits
Description (Default: 0x0004)
[ 15:11 ]
Unused
10
Unit self-test bit (bit reset upon completion of self-test)
0: Disabled (default)
1: Enabled
[ 9:8 ]
Unused
[ 7:3 ]
Unused
2
Data-ready enable bit
0: Disabled
1: Enabled (default)
1
Data-ready line polarity
0: Low upon data-ready (default)
1: High upon data-ready
0
Unused
The self-test enables the system to test individual sensors by applying a temporary bias to
determine if they are responding correctly. Once self-test completes, the self-test bit (bit
10) is reset to indicate that the test is finished. Results of the self-test are store in the
status register, 0x3C. To initiate self-test, the master sends 0xB504 across the SPI bus.
The data-ready bits enable the master to enable or disable the data-ready signal provided
on pin 7 of the DMU380ZA and to set the data-ready signal polarity (high or low). To
enable data-ready with a high signal, the master sends 0xB406.
5.7.2
Output Data Rate/Clock Configuration
Output data rate (ODR) and system clock configuration are combined into a single 16-bit
register at memory location 0x36; individual bits are assigned according to Table 26.
Note: these settings apply only to data output via the DMU380ZA SPI port and do not
affect the low-level UART output port.
Table 26 Output Data Rate/Clock Configuration Register
(Base Address: 0x36), Read/Write
Bits
Description (Default: 0x0101)
[ 15:12 ]
Unused
