PR
EL
IMI
NA
RY
SW71122
MLX71122 RF Receiver
Programming Software Manual
39011 71122 01
Page 15 of 21
SW71122-Manual
Rev. 004
Aug/11
5.3 PLL Control – Tab
The PLL Control tab contains settings for the PLL and the VCO.
5.3.1
LDTIME
This selection box specifies the minimum time delay before a lock in of the PLL occurs after start of the PLL.
It is related to the reference frequency f
R
of the PFD.
Four possible time delays are selectable: 2 / f
R
, 4 / f
R
, 8 / f
R
, 16 / f
R
(default)
5.3.2
LDERR
These radio buttons specify how long the up and down pulses of the PFD can be different without loosing the
lock in state. If the PLL is locked in, these times of different up and down signals should be very small since
there is no correction of the VCO frequency necessary. If not, the power of the reference spurs in the VCO
output signal will increase. This can be the case for leaky capacitors in the loop filter. If the default for
LDERR
of 15ns is not sufficient to keep the lock in state, it can be increased to 30ns.
5.3.3
CPCUR
This selection box specifies the charge pump current which is important to know for the design of the PLL
loop-filter. The charge pump is controlled by a Phase-Frequency-Detector (PFD) that makes it possible to
control phase as well as frequency deviations of the VCO. Four different settings are selectable:
•
100
µ
A
±100
µ
A (default)
•
400
µ
A
±400
µ
A
•
400
µ
A Dn
drains 400
µ
A from pin LF to ground; static down
•
400
µ
A Up
sources 400
µ
A from V
CC
to pin LF; static up
