background image

PR

EL

IMI

NA

RY

SW71122 

MLX71122 RF Receiver 

Programming Software Manual 

 

 
39011 71122 01 

Page 10 of 21  

SW71122-Manual 

Rev. 004 

 

Aug/11 

 

4.6  IC Status - Frame 

 

 

 

 

 
 
The  IC  Status  frame  displays  information  about  the  internal  state  of  the  IC  if  the  Multi  Functional  Output 
(MFO) mode is set to 

SPI out

 (left figure). A click on the Refresh button reads out the data from the MFO-pin 

of the IC. 

 

The following data is displayed: 

 

Field 

Value 

Meaning 

IFFVAL 

Integer number between 0 and 255 

Tuning value of the internal IF filter 

tuned 

Filter tuned or auto-tuning disabled 

tune up 

Tuning up the filter frequency 

tune dn 

Tuning down the filter frequency 

IFFSTATE 

CCO fail 

Master oscillator of filter does not work 

locked 

PLL locked in 

LD 

Not locked 

PLL not locked in 

Low 

V

RSSI

 in lower region 

In range 

V

RSSI

 in mid region 

RSSI 

High 

V

RSSI

 in upper region 

LD Time 

Time in ms 

Approximate PLL lock  time 

 

LD  is  only  displayed  if 

Lock  Detect

  is  selected  in 

function  of  LDRSSIL  bit

  or  MFO-mode  is  set  to  

LD-out

.  In  LD-out  mode  the  additional  field 

LD  Time

  is  displayed

 

(right  figure)  and  the  PLL  lock  in  time  is 

measured every time when data is send to the IC. 
 
 

4.7  Frequency Pre-Selection - Frame 

 

 

 
Four fixed receive frequencies at 315.0MHz, 433.9MHz, 868.3MHz or 915.0MHz can be pre-selected to ease 
the  initialization  of  the  receiver.  All  settings  of  the  receiver  are  affected  and  are  reset  to  their  default  value 
with respect to the receive frequency. 
 

Summary of Contents for MLX71122

Page 1: ...ing Software Manual Software Version v3 2 Software Revision History Software Version Date Changes Doc Rev v2 0 28 08 2006 Initial Version for MLX71122A 001 v2 1 03 01 2007 Adaptation of software to 2nd version of MLX71122A 002 v3 1 10 04 2008 Adaptation of software to 2 nd version of MLX71122B 003 v3 2 26 08 2011 Description for USB SPI converter added 004 ...

Page 2: ...6 IC Status Frame 10 4 7 Frequency Pre Selection Frame 10 5 Description of the Control Tabs 11 5 1 Mode Control Tab 11 5 1 1 Operation Mode 11 5 1 2 Multi Functional Output Mode 12 5 1 3 Function of LDRSSIL bit 12 5 1 4 Bit Slicer Mode 12 5 1 5 DTAO Polarity 12 5 1 6 Demodulation Type 12 5 2 Gain Control Tab 13 5 2 1 LNA 13 5 2 2 IF Filter 13 5 2 3 1st Mixer Gain 13 5 2 4 2nd Mixer Gain 14 5 2 5 D...

Page 3: ...urrent 16 5 3 9 VCO Core Current 16 5 4 Frequency and IFF Control Tab 17 5 4 1 Auto Adjustment 17 5 4 2 Halt 17 5 4 3 RIFF Divider 17 5 4 4 IFF Preset Value 18 5 4 5 IFF centre freq 18 5 4 6 fXTAL 18 5 4 7 R Divider 18 5 4 8 fRF 18 5 4 9 A 18 5 4 10 N 18 5 4 11 NTOT 18 5 4 12 Calculate Button 18 5 4 13 LO1 19 5 4 14 LO2 19 5 4 15 LO2DIV 19 5 5 Register Set Tab 19 ...

Page 4: ...hree pins A SCLK B SDTA and C SDEN A block diagram of the receiver is shown below The following tables show the functionality of the three digital control pins that are used for general operating mode selection Pin Value Function 0 ABC mode stand alone mode 8 pre defined frequencies SPISEL 1 SPI mode programmable mode full control via SPI Pin Value SPISEL Function 0 FSK receive mode 0 1 no effect ...

Page 5: ... pin2 C SDEN pin17 Connected 5 If the PC s USB port is used a USB SPI converter is required It is available on request or can be purchased together with the evaluation board EVB71122 Note that pin 7 of the MLX71122 SPISEL is connected to logic HIGH on the EVB71122 This is to set the receiver to SPI mode 3 Installation and Files The installation program will ask you for a folder where you want to i...

Page 6: ...ble are con nected to the PC This ensures that the software automatically detects whether the USB or the LPT port are used The software can be started by double clicking on the main program icon in the installation directory or by double clicking on the link During start up the software reads out the corresponding init file and restores all settings that were active when the software was regularly...

Page 7: ...SB SPI converter has been found 4 2 3 Settings The menu Settings contains three menu items Defaults restores the state that is hard coded on the MLX71122 ext Vref SPI logical high level set by external reference voltage e g provided by supply voltage of EVB71122 Set Vpwm SPI logical high level set by internal reference voltage The Defaults menu item of this menu restores the state that is hard cod...

Page 8: ...9011 71122 01 Page 8 of 21 SW71122 Manual Rev 004 Aug 11 4 2 4 About This menu displays a window with information about the LPT port to pin connections This menu displays a window with information about the USB SPI converter only available if the USB SPI converter is used ...

Page 9: ...ter the first mixer fIF2 second intermediate frequency after the second mixer fLO1 VCO output frequency or LO input frequency of first mixer fLO2 LO input frequency of second mixer depends on fLO1 fPFD working frequency of the phase frequency detector of the PLL All frequencies are given in MHz with three post decimal positions 4 5 Program Status Line The Status Line at the bottom of the program w...

Page 10: ... the filter frequency IFFSTATE CCO fail Master oscillator of filter does not work locked PLL locked in LD Not locked PLL not locked in Low VRSSI in lower region In range VRSSI in mid region RSSI High VRSSI in upper region LD Time Time in ms Approximate PLL lock time LD is only displayed if Lock Detect is selected in function of LDRSSIL bit or MFO mode is set to LD out In LD out mode the additional...

Page 11: ...m and reference oscillator are working Synthesizer only only biasing system reference oscillator and PLL are working The first operation mode consumes virtually no current The circuit is dead except of the SPI that can listen to commands In Receive mode all necessary blocks are turned on to receive data at the programmed frequency The last two operation modes can be used to accelerate the start up...

Page 12: ...the state of the PLL can be detected The lock state is also displayed in the LD field of the IC Status frame An additional field in the IC Status frame appears that can display the approximate lock in time in ms measured by the PC This is not very accurate In SPI out mode the data of register R7 can be read out and the different circuit states are displayed in the IC Status frame 5 1 3 Function of...

Page 13: ...the default gain are selectable The gain is controlled by the core current of the LNA Possible selections are Default 20dB Default 6dB Default 2dB Default 5 2 2 IF Filter The Intermediate Frequency Filter IFF has four gain settings 14dB 6dB 0dB default 6dB These are absolute voltage gains from the filter input to the input of the Intermediate Frequency Amplifier IFA Default gain is 6dB If MFO is s...

Page 14: ...ble First the gain of mixer 2 is lowered then mixer 1 and in the end the LNA gain 5 2 6 RSSI Gain The RSSIGAIN setting determines the RSSI gain of the IFA low 39mV dB high 51mV dB default The output voltage range of the RSSI voltage will also be affected by this setting 5 2 7 Enable AGC This checkbox enables or disables default the AGC feature Make sure that RSSIGAIN is high to use AGC 5 2 8 Delay...

Page 15: ...e times of different up and down signals should be very small since there is no correction of the VCO frequency necessary If not the power of the reference spurs in the VCO output signal will increase This can be the case for leaky capacitors in the loop filter If the default for LDERR of 15ns is not sufficient to keep the lock in state it can be increased to 30ns 5 3 3 CPCUR This selection box sp...

Page 16: ... teristic changes the sign of its slope then it is necessary to change the PDF polarity This can be the case if an external VCO is used or if an additional element with controllable reactance is connected between the pins TNK1 and TNK2 5 3 7 VCO Range The MLX71122 is designed for VCC 5V so the default value of this setting is 5V Nevertheless it can be used down to 3V if this value is set to 3V The...

Page 17: ...cil lator The tab offers several fields to control the adjustment circuit 5 4 1 Auto Adjustment This checkbox controls whether the auto adjustment is turned on or off If it is turned on default it corrects continuously the centre frequency of the filter If it is turned off then the actual IFF Preset Value is loaded into the digital control word and the auto tuning stops with this value The filter ...

Page 18: ...der This is the reference divider value by that the RO frequency is divided to provide the reference frequency for the PFD Default value is 75 5 4 8 fRF It is possible to enter the desired receive frequency in this field The N and A counter values are calculated from this entry when the calculate button is pressed Default receive frequency is 384MHz 5 4 9 A This is the A counter of the pulse swall...

Page 19: ...O2 setting can be observed in the Tuning Info frame see figure in section 4 4 5 4 15 LO2DIV These radio buttons specify the divider ratio by that the LO2 frequency is lower than the LO1 frequency LO1 is injected into mixer 1 and LO2 is injected into mixer 2 5 5 Register Set Tab The Register Set tab gives an overview of all actual control word registers of the IC see Data Sheet section 4 Registers ...

Page 20: ...PRELIMINARY SW71122 MLX71122 RF Receiver Programming Software Manual 39011 71122 01 Page 20 of 21 SW71122 Manual Rev 004 Aug 11 Your Notes ...

Page 21: ...ev 004 Aug 11 For the latest version of this document go to our website at www melexis com Or for additional information contact Melexis Direct Europe and Japan All other locations Phone 32 1367 0495 Phone 1 603 223 2362 E mail sales_europe melexis com E mail sales_usa melexis com ISO TS16949 and ISO14001 Certified ...

Reviews: