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Page 6

3 Precision Time Protocol (PTP) / IEEE1588

The Time Stamp Unit, integrated in an FPGA (Field Programmable Gate Array, a programmable logic device),

checks the data trac on the MII-interface between the PHY receiver (physical connection to the network) and

the Ethernet controller (MAC) on the PTP module. If a valid PTP packet is detected, the time stamp unit takes

a time stamp of that packet which is read by a single board computer (SBC) running the PTP software. The

conguration and status trac between the PTP board and main SBC is done over a USB connection.

3.2 Functionality in Master Systems

10/100MBit

LAN

10 Mhz from GPS

RJ45 with

magnetics

and LEDs

PHYceiver

MAC

controller

USB hub

FPGA

microcontroller
with integrated

progr. memory

10M/activity

100M/activity

Rx/Tx

MII interface

USB

USB 1.1
to computer 
module

Time Stamp Unit PTP Master

FPGA

configuration

memory

PPS from GPS

control

adr/data

control

data

USB

After power up, the module accepts the absolute time information (PTP seconds) of a reference time source

(GPS reference clock) only once, and the PTP nanoseconds are set to zero. If the oscillator frequency of the

reference time source has reached its nominal value, the nanoseconds are reset again. This procedure leads to a

maximum deviation of 20 nsec of the pulse per second (1PPS) of the PTP Master compared to the 1PPS of the

GPS reference clock. The reference clock of the PTP board's time stamp unit (50 MHz) is derived from the GPS

disciplined oscillator of the reference time source using a PLL (Phase Locked Loop) of the FPGA. The achieves

a direct coupling of the time stamp unit to the GPS system.

3.3 Functionality in Slave Systems

10/100MBit

LAN

10 MHz

PPS

programmable

outputs

modulated

time code

RJ45 with

magnetics

and LEDs

PHYceiver

MAC

controller

USB hub

status LEDs

driver

 circuits

FPGA

filter and

driver circuit

oscillator

DAC

microcontroller
with integrated

progr. memory

FPGA

configuration

memory

10M/activity

100M/activity

Rx/Tx

MII interface

USB

USB

data

control

control

control 
voltage

PWM time code

clock

adr/data

control

USB 1.1
to computer 
module

clock

status

Time Stamp Unit PTP Slave

After decoding valid time information from a PTP Master, the system sets its own PTP seconds and nanoseconds

accordingly. The PTP oset calculated by the PTP driver software of the single board computer is used to adjust

the master oscillator of the TSU-USB. This allows the PTP Slave to generate very high accuracy output signals

(10 MHz/1PPS/IRIG).

6

Date: 22nd November 2012

PTP270PEX

Summary of Contents for PTP270PEX

Page 1: ...MANUAL PTP270PEX IEEE 1588 Computer Clock 22nd November 2012 Meinberg Radio Clocks GmbH Co KG...

Page 2: ......

Page 3: ...7 3 4 4 Two Step or One Step 8 3 4 5 End To End E2E or Peer To Peer P2P Delay Measurements 8 3 4 6 Mode Recommendations 8 3 4 7 Message Rate Settings 8 3 4 8 ANNOUNCE Messages 9 3 4 9 SYNC FOLLOWUP M...

Page 4: ...nberg Radio Clocks GmbH Co KG Lange Wand 9 31812 Bad Pyrmont Germany Phone 49 0 52 81 93 09 0 Fax 49 0 52 81 93 09 30 Internet http www meinberg de Mail info meinberg de Date 2010 06 08 PTP270PEX Date...

Page 5: ...stalling the driver correctly 2 2 Mode of operation The on board Time Stamp Unit TSU integrated in a FPGA Field Programmable Gate Array programmable logic device monitors the data tra c on the MII int...

Page 6: ...r a continuous stream of events at a lower rate depending on the transmission speed of COM1 can be measured The format of the output string is described in the technical speci cations at the end of th...

Page 7: ...RJ45 with magnetics input signals time capture output signals signal generator PCI Express Bus register set single board computer SBC running PTP stack microcontroller reference oscillator O T CXO Tx...

Page 8: ...egrade the accuracy therefore classic layer 2 and 3 Ethernet switches with their store and forward technology are not suitable for PTP networks and should be avoided With activating the HQ Filter see...

Page 9: ...reached its nominal value the nanoseconds are reset again This procedure leads to a maximum deviation of 20 nsec of the pulse per second 1PPS of the PTP Master compared to the 1PPS of the GPS referen...

Page 10: ...hronization link 3 4 2 Network Layer 2 or Layer 3 PTP IEEE 1588 2008 o ers a number of so called mappings on di erent network communication layers For Meinberg products you can choose between running...

Page 11: ...s to be redirected and ows into the other direction A PTP slave in a sync infrastructure using E2E would in this case apply the wrong delay correction calculations until it performs the next delay mea...

Page 12: ...clock or the primary one during initialization the devices re quire to receive at least two consecutive ANNOUNCE messages Continuing our example it would take the 6 seconds to determine that the curre...

Page 13: ...the term jitter is used to describe the maximum deviation of the measured o sets around a certain mean value This time jitter of standard non PTP compliant switches can be in the range of 100 ns up to...

Page 14: ...direction Higher bandwith is implemented by using multiple lanes silmutaneously A PCI Express x16 slot for example uses sixteen lanes providing a data volume of 4 GB s For comparison when using conve...

Page 15: ...switch assigned are always available at the connector D SUB Pin Signal Signal level DIL switch 1 VCC out 5V 1 1 PPO0 out RS232 8 2 RxD in res RS232 3 TxD out res RS232 4 PPO1 out TTL 5 4 10MHz out TT...

Page 16: ...detected and the LED TX ashes whenever an outgoing PTP packet is detected by the Time Stamp Unit The 9 pin sub D connector is wired to the PTP270PEX s serial port COM0 Pin assignment can be seen in t...

Page 17: ...timecodes which are transmitted by modulating the pulse dura tion of a DC signal TTL in case of PTP270PEX see chapter IRIG standard format for details Transmission of the time code is synchronized to...

Page 18: ...7 3 IRIG Standard Format Page 15 7 3 IRIG Standard Format PTP270PEX Date 22nd November 2012 15...

Page 19: ...Page 16 7 Time codes 7 4 AFNOR Standard Format 16 Date 22nd November 2012 PTP270PEX...

Page 20: ...T Daylight Saving Time set during daylight saving time 64 Timezone O set Sign sign of TZ o set 0 1 65 TZ O set binary encoded 1 66 TZ O set binary encoded 2 O set from IRIG time to UTC time 67 TZ O se...

Page 21: ...L level ACCURACY OF PULSES depending on master oscillator TCXO OCXO LQ better than 100 nsec after synchronization and 20 minutes of operation OCXO MQ OCXO HQ better than 20 nsec after synchronization...

Page 22: ...emperature dependant dri free run 1 10 6 20 70 C 2 10 7 0 60 C Note 1 The accuracy in Hertz is based on the standard frequency of 10 MHz For example Accuracy of TCXO free run one day is 1 10 E 7 10 MH...

Page 23: ...t rungen von A1 2000 A2 2003 informationstechnischen Einrichtungen Limits and methods of measurement of radio interference characteristics of information technology equipment EN55024 1998 Grenzwerte u...

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