MeiG_SLM550_Hardware Design Manual
MeiG Smart Technology Co., Ltd
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MIPI_CSI1_LANE2_P
73
I/O
MIPI_CSI1_LANE3_M
70
I/O
MIPI_CSI1_LANE3_P
71
I/O
GPIO21_MCAM_MCLK0
74
O
Main camera clock signal
GPIO19_MCAM_RST_N
79
O
Main camera reset signal
GPIO25_MCAM_PWDN
80
O
Main camera sleep signal
GPIO29_CAM_I2C_SDA0
84
I/O
I2C data
GPIO30_CAM_I2C_SCL0
83
I/O
I2C clock
Extra LDO
1.8V IOVDD
VREG_L20_2P85
129
O
2.8V AFVDD
Extra LDO
2.8V AVDD
Extra LDO
1.2V DVDD
Extra LDO
1.2V DVDD
Sub camera interface
Name
Pin
Input/output
Description
MIPI_CSI0_CLK_M
157
I
Sub camera MIPI clock signal
MIPI_CSI0_CLK_P
196
I
MIPI_CSI0_LANE0_M
158
I/O
Sub camera MIPI data signal
MIPI_CSI0_LANE0_P
197
I/O
MIPI_CSI0_LANE1_M
159
I/O
MIPI_CSI0_LANE1_P
198
I/O
MIPI_CSI0_LANE2_M
160
I/O
MIPI_CSI0_LANE2_P
199
I/O
MIPI_CSI0_LANE3_M
161
I/O
