CHAPTER 3
AWARD
®
BIOS SETUP
3-16
Passive Release
When Enabled, CPU to PCI bus accesses are allowed during
passive release. Otherwise, the arbiter only accepts another PCI master
access to local DRAM. The settings are Enabled or Disabled.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1. The settings are Enabled or Disabled.
AGP Aperture Size (MB)
Select the size of the Accelerated Graphics Port (AGP) aperture.
The aperture is a portion of the PCI memory address range dedicated for
graphics memory address space. Host cycles that hit the aperture range are
forwarded to the AGP without any translation.