MAXDATA BELINEA 101705, Service Manual

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Belinea 101705 (111723) Service Manual
-15- 4/22/2004
7. WORKING THEOREM
A. Scaling controller
The ADC is to convert RGB analog signal to digital signal that scaling chip can acknowledge.
The HSYNC input receives a logic signal and provides the frequency reference for pixel clock
generation.
The scaling IC is to converts the input signal ranging from VGA to SXGA into SXGA resolution
that panel can acknowledge.
GENERAL DESCRIPTION
The MST8116A is a high performance, and fully integrated graphics processing IC solution for
LCD monitors with resolutions up to SXGA. It is configured with an integrated triple-ADC/PLL, a
high quality scaling engine, an on-screen display controller, a built-in output clock generator, a
panel timing controller (TCON), and RSDS display interface. To further reduce system costs, the
MST8116A also integrates intelligent power management control capability for green-mode
requirements and spread-spectrum support for EMI management.
PIN DESCRIPTION
CPU Interface
Pin Name Pin Type Function Pin
HWRESET Schmitt Trigger Input
w/ 5V-tolerant Hardware reset; active high 32
CS Input w/ 5V-tolerant 3 Wire Serial Bus Chip Select; active high 69
SDA I/O w/ 5V-tolerant 3 Wire Serial Bus Data; 4mA driving strength 70
SCL Input w/ 5V-tolerant 3 Wire Serial Bus Clock 71
INT Output CPU interrupt; 4mA driving strength 72
Analog Interface
Pin Name Pin Type Function Pin
HSYNC0 Schmitt Trigger Input
w/ 5V-tolerant Analog HSYNC input 37
VSYNC0 Schmitt Trigger Input
w/ 5V-tolerant Analog VSYNC input 38
REFP Internal ADC top de-coupling pin 66
REFM Internal ADC bottom de-coupling pin 67
RIN0 Analog Input Analog red input 63
RIN0M Analog Input Reference ground for analog red input 62
SOGIN0 Analog Input Sync-on-green input 61
GIN0 Analog Input Analog green input 60
GIN0M Analog Input Reference ground for analog green input 59
BIN0 Analog Input Analog blue input 58
BIN0M Analog Input Reference ground for analog blue input 57
REXT External resistor 390 ohm to AVDD 52
RSDS Interface
Pin Name Pin Type Function Pin
CLKAP Output A-Link Positive RSDS Differential Clock Output from
“
Odd
”
Channel 118
CLKAN Output A-Link Negative RSDS Differential Clock Output from
“
Odd
”
Channel 119
CLKBP Output B-Link Positive RSDS Differential Clock Output from
“
Even
”
Channel 120
CLKBN Output B-Link Negative RSDS Differential Clock Output from
“
Even
”
Channel 121
BA[3:1]P Output A-Link Positive RSDS Differential Data Output from
“
Odd
”
Channel 92, 90, 88
BA[3:1]N Output A-Link Negative RSDS Differential Data Output from
“
Odd
”
Channel 93, 91, 89
GA[3:1]P Output A-Link Positive RSDS Differential Data Output from
“
Odd
”
Channel 102, 100, 98
GA[3:1]N Output A-Link Negative RSDS Differential Data Output from
“
Odd
”
Channel103, 101,99
RA[3:1]P Output A-Link Positive RSDS Differential Data Output from
“
Odd
”
Channel 112, 110, 108
RA[3:1]N Output A-Link Negative RSDS Differential Data Output from
“
Odd
”
Channel 113, 111, 109
BB[3:1]P Output B-Link Positive RSDS Differential Data Output from
“
Even
”
Channel 4, 128, 124
BB[3:1]N Output B-Link Negative RSDS Differential Data Output from
“
Even
”
Channel 5, 1, 125
GB[3:1]P Output B-Link Positive RSDS Differential Data Output from
“
Even
”
Channel 14, 12, 8
GB[3:1]N Output B-Link Negative RSDS Differential Data Output from
“
Even
”
Channel 15, 13, 9
RB[3:1]P Output B-Link Positive RSDS Differential Data Output from
“
Even
”
Channel 24, 22, 16
RB[3:1]N Output B-Link Negative RSDS Differential Data Output from
“
Even
”
Channel 25, 23, 17
GPO[8:5] Output TCON GPO[8:5]; 4mA driving strength 29, 28, 30,31
GPO[4:0] Output w/ Pull-down TCON GPO[4:0]; 4~12mA driving strength programmable 79-83
OINV Output w/ Pull-down Resistor TCON
“
Odd
”
Channel Inversion; 4~12mA driving strength
programmable 78