60 Appendix B: Technical information
• Has 2 Gbytes of DDR3 SDRAM, which it uses as main on-board memory
(acquisition and processing). Total memory bandwidth of 12.8 Gbytes/sec.
• Optionally has 4 banks of QDR-II SRAM that total 16 or 32 Mbytes of memory,
which it uses as dedicated Processing FPGA memory. Total memory bandwidth
of up to 4.0 Gbytes/sec in each direction.
• Has one UART per acquisition path.
• Supports input from an external 3.3 V LVDS rotary encoder with quadrature
output per acquisition path.
• Has four camera control signals (re-routing of specific auxiliary input signals,
HSYNC output, VSYNC output, clock output, timer output, or user output)
*
per acquisition path.
• Has up to 16 auxiliary signals that can be path independent or path dependent,
depending on the functionality
†
selected
*
. When path dependent, there are:
- Three TTL auxiliary I/O signals (trigger input or user input, or timer output
or user output) per acquisition path.
- One LVDS auxiliary output signal (timer output or user output) per acquisition
path.
- Two LVDS auxiliary input signals (trigger input, timer-clock input, quadrature
input, or user input) per acquisition path.
- Two opto-isolated auxiliary input signals (trigger input or user input) per
acquisition path.
*. See the
Camera control and auxiliary signals
section section in
RadientPro CL hardware reference
chapter for supported functionality.
†. For example, for Matrox RadientPro CL-DB, TTL_AUX_IO_14 can be used as a
trigger input when grabbing from either acquisition path; however, you can only route
timer 2 of acquisition path 1 to TTL_AUX_IO_14.
