Marvin Test Solutions GX5280, User Manual

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22 GX5280 User Guide
Clock and Strobe Signals
The clock (CLK) signal initiates each output vector. The rate of this signal can be programmed from 5Hz to
100MHz. Similarly, the strobe signal latches the input vector. All clock and strobe signals are distributed to all
DIOs.
The GX5280’s clock architecture provides the user with the flexibility to align signals between the DIO and the Unit
Under Test (UUT) using delay settings. Figure 4-3 is a block diagram of the clock architecture which includes
programmable delays for the DIO clock and strobe. The clock signal is used to output test vectors, and strobe
(clock) data into the DIO’s record memory. The basic architecture of the clock delay generator provides seven
coarse delays in 4 ns steps. In addition a fine resolution delay (vernier) is available which provides a 0ns to 3ns
delay in 250ps steps. Together, these elements provide delays in the range of 0ns to 27ns, with 250ps resolution for
the data out and data input clocks.
PXI 10 MHz
External Clock (J3-P31)
B Clock Out (J3-P20)
External Strobe (J3-P32)
0 - 3nS, 250pS Steps
4 - 7nS, 250pS Steps
8 - 11nS, 250pS Steps
12 - 15nS, 250pS Steps
16 - 19nS, 250pS Steps
20 - 23nS, 250pS Steps
24 - 27nS, 250pS Steps
Clock/Strobe Delay Range
PLL Reference Source
Clock
Source
Strobe
Source
4nS
8nS
12nS
20nS
24nS
16nS
Fixed Delay
Clock Delay Tap
0nS
4nS
8nS
12nS
20nS
24nS
16nS
Fixed Delay
0nS
Strobe Delay Tap
Clock Out (OClk J3-P22)
Stimulus
Output
Register
Output Data
/ 32
To Pin Drivers
Strobe Out (Ostrb J3-P24)
Response
Input
Register
Input Data
/ 32
From Pin Receivers
I/O PLL
Clock
In
Programmable
Strobe Clock Delay
(0-3nS, 250pS Steps)
Programmable
Board Delay
(+/- 3nS, 250pS
Steps)
Programmable
B-Clock Delay
(0-3nS, 250pS Steps)
Programmable
I/O Clock Delay
(0-3nS, 250pS Steps)
CLK
Figure 4-3: Clock Source Block Diagram