Chapter 4 - Theory of Operation
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Chapter 4 - Theory of Operation
This chapter presents the theory of operation for the GX5280 boards, with an overview of operation and a simple
description of operation for one channel (I/O pin). Other topics covered in this chapter are:
Architecture Diagram.
Operation of clock (CLK) and strobe signals.
Memory management.
Vector Program Control.
Basic states of operation.
Trigger operation.
Pause operation.
Architecture
The GX5280 can run at frequencies as high as 200MHz (See specifications) feature three deep onboard memory
options: 32, 64, or 128 Mbit/Channel. Each board contains 32 I/O pins arranged in 4 groups of 8, each group having
its own direction either input or output applied to all steps in the group. The I/O stage can be software-configured to
interface with a broad set of common logic families of 5,0 V, 3,3 V, 2,5 V and 1,8 V. as well as additional dedicated
LVDS I/O stage connector. In addition the I/O voltage stage can be programmed with 10 mV resolution ranges from
1.4V to 3.6V. The programmed voltage level determines the logic high level for channels programmed to output
mode and defines the threshold level for channels defined as input.
The GX5280 works as a complex programmable state machine with three main states:
HALT
,
PAUSE
and
RUN
.
The central module of the board is the Vector Program Control. The Vector Program Control interprets predefined
commands, controls the states machine and monitors the complex Trigger/Pause mechanism.
External control provides CLK, strobe and I/O pin direction from an external source. The combination of the
external bi-directional control and external clocking, strobing, and triggering provides the capability to fully
synchronize with UUTs and to minimize initialization procedures. The board sequencer permits the creation of
conditional and unconditional loops and branches to manipulate the output vectors. This provides the capability to
generate indefinite stimulus vectors at the maximum test rate.
Summary of Contents for GX5280
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