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88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

Doc. No. MV-S105540-00, Rev. --

Copyright © 2009 Marvell

Page 14

Document Classification: Proprietary Information

March 4, 2009, Advance

C5
A2
A1
C4
B3
C3
D3
B2

86
87
89
90
91
93
92
95

120
121
123
124
125
126
128
3

RXD[7]
RXD[6]
RXD[5]
RXD[4]
RXD[3]/RXD[3]
RXD[2]/RXD[2]
RXD[1]/RXD[1]
RXD[0]/RXD[0]

O, Z

GMII and MII Receive Data. Symbols
received on the cable are decoded and pre-
sented on RXD[7:0] in 1000BASE-T mode.

In MII mode, RXD[3:0] are used in
100BASE-TX and 10BASE-T modes. In MII
mode, RXD[7:4] are driven low.

RXD[7:0] is synchronous to RX_CLK.

B5

84

115

CRS

O, Z

GMII and MII Carrier Sense. CRS asserts
when the receive medium is non-idle. In half-
duplex mode, CRS is also asserted during
transmission. CRS assertion during half-
duplex transmit can be disabled by program-
ming register 16.11 to 0.

CRS is asynchronous to RX_CLK,
GTX_CLK, and TX_CLK.

B6

83

114

COL

O, Z

GMII and MII Collision. In 10/100/
1000BASE-T full-duplex modes, COL is
always low. In 10/100/1000BASE-T half-
duplex modes, COL asserts only when both
the transmit and receive media are non-idle.

In 10BASE-T half-duplex mode, COL is
asserted to indicate signal quality error
(SQE). SQE can be disabled by clearing reg-
ister 16.2 to zero.

COL is asynchronous to RX_CLK,
GTX_CLK, and TX_CLK.

Table 2:

GMII/MII Interfaces (Continued)

117-TFBGA
Pin #

96-BCC
Pin #

128-PQFP
Pin #

Pin Name

Pin
Type

Description

«
...
12
13
14
15
16
...
»

Summary of Contents for Alaska Ultra 88E1111

Page 1: ...Marvell Moving Forward Faster Doc No MV S105540 00 Rev March 4 2009 Document Classification Proprietary Information 88E1111 Product Brief Integrated 10 100 1000 Ultra Gigabit Ethernet Transceiver ...

Page 2: ...ailed Do not use Marvell products in these types of equipment or applications With respect to the products described herein the user or recipient in the absence of appropriate U S government authorization agrees 1 Not to re export or release any such information consisting of technology software or source code controlled for national security reasons by the U S Export Control Regulations EAR to a ...

Page 3: ...vice may be used to implement 1000BASE T Gigabit Interface Converter GBIC or Small Form Factor Pluggable SFP modules The 88E1111 device uses advanced mixed signal pro cessing to perform equalization echo and crosstalk cancellation data recovery and error correction at a gigabit per second data rate The device achieves robust performance in noisy environments with very low power dissipation The 88E...

Page 4: ...E1111 RGMII GMII MAC to SGMII MAC Conversion M a g n e t i c s MAC Interface Options GMII MII TBI RGMII RTBI SGMII Serial Interface Media Types 10BASE T 100BASE TX 1000BASE T RJ 45 10 100 1000 Mbps Ethernet MAC 88E1111 Device Serial Interface MAC Interface Options GMII MII RGMII Media Types 1000BASE X Fiber Optics 10 100 1000 Mbps Ethernet MAC 88E1111 Device Serial Interface 4 pin SGMIII MAC Inter...

Page 5: ...s Test or Reset Modes 33 1 6 117 Pin TFBGA Pin Assignment List Alphabetical by Signal Name 34 1 7 96 Pin BCC Pin Assignment List Alphabetical by Signal Name 36 1 8 128 Pin PQFP Pin Assignment List Alphabetical by Signal Name 38 2 1 117 pin TFBGA Package 40 2 2 96 pin BCC Package Top View 42 2 3 96 Pin BCC Package Bottom View 43 2 4 128 Pin PQFP Package 44 3 1 Ordering Part Numbers and Package Mark...

Page 6: ...000 A B RX_DV RXD0 RXD3 VDDO CRS COL AVDD LED_ LINK100 VDDOH B C RX_CLK VDDO RXD2 RXD4 RXD7 DVDD DVDD LED_ LINK10 LED_RX C D TX_CLK RX_ER RXD1 VSS VSS VSS DVDD CONFIG 0 LED_TX D E TX_EN GTX_CLK DVDD VSS VSS VSS DVDD LED_ DUPLEX CONFIG 1 E F TXD0 TX_ER DVDD VSS VSS VSS VDDOH CONFIG 2 CONFIG 4 F G NC TXD1 TXD2 VSS VSS VSS CONFIG 3 CONFIG 6 CONFIG 5 G H TXD4 TXD3 TXD5 VSS VSS VSS VSSC SEL_ FREQ XTAL1...

Page 7: ...I 2 MDI 3 MDI 3 TDI AVDD TMS TRSTn VDDOX TCK TDO VDDOH VSSC XTAL2 XTAL1 SEL_ FREQ DVDD CONFIG 6 CONFIG 5 CONFIG 4 CONFIG 3 DVDD CONFIG 2 CONFIG 1 CONFIG 0 VDDOH DVDD LED_TX LED_RX LED_DUPL EX DVDD VDDOH LED_LINK 1000 VDDO RXD0 RX_DV RXD2 RXD1 RXD3 RXD4 RXD5 RXD6 DVDD COL S_IN S_CLK S_OUT S_OUT LED_LINK 100 VDDO RXD7 CRS S_IN S_CLK AVDD LED_LINK 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20...

Page 8: ...09 108 107 106 105 104 103 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VSS AVDD VSS S_OUT VSS S_CLK S_CLK VSS S_IN S_IN COL CRS VSS DVDD DVDD VSS RXD7 RXD6 VDDO RXD5 RXD4 RXD3 RXD2 VSS RXD1 AVDD VSS MDI 3 MDI 3 VSS AVDD VSS MDI 2 MDI 2 VSS HSDAC HSDAC AVDD VSS NC AVDD VSS MDI 1 MDI 1 VSS AVDD VSS MDI 0 MDI 0 VSS RSET VSS VSS LED_LINK10 LED_LINK100 LED_LINK1000 VDD...

Page 9: ...etary Information Page 9 Signal Description Pin Description 1 4 Pin Description 1 4 1 Pin Type Definitions Pin Type Definition H Input with hysteresis I O Input and output I Input only O Output only PU Internal pull up PD Internal pull down D Open drain output Z Tri state output mA DC sink capability ...

Page 10: ...spond to BI_DA In MDIX configuration MDI 0 correspond to BI_DB In 100BASE TX and 10BASE T modes in MDI configuration MDI 0 are used for the transmit pair In MDIX configuration MDI 0 are used for the receive pair MDI 0 should be tied to ground if not used N3 N4 33 34 46 47 MDI 1 MDI 1 I O D Media Dependent Interface 1 In 1000BASE T mode in MDI configuration MDI 1 correspond to BI_DB In MDIX configu...

Page 11: ...ion MDI 2 corresponds to BI_DD In 100BASE TX and 10BASE T modes MDI 2 are not used MDI 2 should be tied to ground if not used N8 N9 42 43 61 62 MDI 3 MDI 3 I O D Media Dependent Interface 3 In 1000BASE T mode in MDI configuration MDI 3 correspond to BI_DD In MDIX configuration MDI 3 correspond to BI_DC In 100BASE TX and 10BASE T modes MDI 3 are not used MDI 3 should be tied to ground if not used T...

Page 12: ... MHz clock reference for TX_EN TX_ER and TXD 3 0 in 100BASE TX mode and a 2 5 MHz clock reference in 10BASE T mode TX_CLK provides a 25 MHz 2 5 MHz or 0 MHz clock during 1000 Mbps Good Link Auto Negotiation and Link Lost states depending on the setting of register 20 6 4 The 2 5 MHz clock is the default rate which may be programmed to another frequency by writing to register 20 6 4 E1 9 16 TX_EN I...

Page 13: ... 4 should be tied low if not used e g RGMII mode C1 2 7 RX_CLK O Z GMII and MII Receive Clock RX_CLK pro vides a 125 MHz clock reference for RX_DV RX_ER and RXD 7 0 in 1000BASE T mode a 25 MHz clock reference in 100BASE TX mode and a 2 5 MHz clock reference in 10BASE T mode TX_TCLK comes from the RX_CLK pins used in jitter testing Refer to Register 9 for jitter test modes B1 94 4 RX_DV O Z GMII an...

Page 14: ...CLK B5 84 115 CRS O Z GMII and MII Carrier Sense CRS asserts when the receive medium is non idle In half duplex mode CRS is also asserted during transmission CRS assertion during half duplex transmit can be disabled by program ming register 16 11 to 0 CRS is asynchronous to RX_CLK GTX_CLK and TX_CLK B6 83 114 COL O Z GMII and MII Collision In 10 100 1000BASE T full duplex modes COL is always low I...

Page 15: ...BI Transmit Data TXD 7 0 presents the data byte to be transmitted onto the cable TXD 9 0 are synchronous to GTX_CLK Inputs TXD 7 4 should be tied low if not used e g RTBI mode E1 9 16 TX_EN TXD8 I TBI Transmit Data In TBI mode TX_EN is used as TXD8 TXD 9 0 are synchronous to GTX_CLK F2 7 13 TX_ER TXD9 I TBI Transmit Data In TBI mode TX_ER is used as TXD9 TXD 9 0 are synchronous to GTX_CLK TX_ER sh...

Page 16: ...d RCLK1 B5 84 115 CRS COMMA O Z TBI Valid Comma Detect In the TBI mode CRS is used as COMMA B6 83 114 COL LPBK I TBI Mode Loopback In the TBI mode COL is used to indicate loopback on the TBI When a 0 1 transition is sampled on this pin bit 0 14 is set to 1 When a 1 0 is sampled on this pin bit 0 14 is reset to 0 If this feature is not used the COL pin should be driven low on the board This pin sho...

Page 17: ...modes the trans mit data nibble is presented on TXD 3 0 on the rising edge of GTX_CLK E1 9 16 TX_EN TX_CTL I RGMII Transmit Control In RGMII mode TX_EN is used as TX_CTL TX_EN is pre sented on the rising edge of GTX_CLK A logical derivative of TX_EN and TX_ER is presented on the falling edge of GTX_CLK C1 2 7 RX_CLK RXC O Z RGMII Receive Clock provides a 125 MHz 25 MHz or 2 5 MHz reference clock w...

Page 18: ...CLK and bits 8 5 presented on the falling edge of GTX_CLK In this mode TXD 7 4 are ignored E1 9 16 TX_EN TD4_TD9 I RTBI Transmit Data In RTBI mode TX_EN is used as TD4_TD9 TD4_TD9 runs at a double data rate with bit 4 presented on the rising edge of GTX_CLK and bit 9 presented on the falling edge of GTX_CLK C1 2 7 RX_CLK RXC O Z RTBI Receive Clock provides a 125 MHz ref erence clock with 50 ppm to...

Page 19: ...ped ance by setting register 26 6 The input impedance default setting is determined by the 75 50 OHM configuration pin A5 A6 79 80 110 109 S_CLK S_CLK I O SGMII 625 MHz Receive Clock For Serial Interface modes HWCFG_MODE 3 0 1x00 the S_CLK pins become Signal Detect SD inputs A7 A8 77 75 107 105 S_OUT S_OUT O Z SGMII Receive Data 1 25 GBaud output Positive and Negative Output impedance on the S_OUT...

Page 20: ...mped ance by setting register 26 6 The input impedance default setting is determined by the 75 50 OHM configuration pin A5 A6 79 80 110 109 S_CLK SD S_CLK SD I Signal Detect input For Serial Interface modes the S_CLK pins become Signal Detect SD inputs A7 A8 77 75 107 105 S_OUT S_OUT O Z 1 25 GHz output Positive and Negative When this interface is used as a MAC inter face S_OUT connects to the MAC...

Page 21: ...nection 1 Copper link down 0 Copper link up D3 92 128 RXD 1 O Z Serial MAC interface PHY_SIGDET 1 con nection 1 S_OUT valid code groups according to clause 36 0 S_OUT invalid B2 95 3 RXD 0 O Z Serial MAC interface PHY_SIGDET 0 con nection 1 S_OUT invalid 0 S_OUT valid code groups according to clause 36 Table 7 1 25 GHz Serial High Speed Interface Continued 117 TFBGA Pin 96 BCC Pin 128 PQFP Pin Pin...

Page 22: ...d out of the device synchronously to MDC This pin requires a pull up resistor in a range from 1 5 kohm to 10 kohm L1 23 32 INTn D The polarity of the INTn pin may be pro grammed at hardware reset by setting the INT_POL bit Polarity 0 Active High 1 Active Low Table 9 Two Wire Serial Interface 117 TFBGA Pin 96 BCC Pin 128 PQFP Pin Pin Name Pin Type Description L3 25 35 MDC SCL I Two Wire Serial Inte...

Page 23: ...100 O mA Parallel LED output for 100BASE TX link or speed This active low LED pin may be pro grammed in direct drive or combined LED modes by programming register LED_LINK Control register 24 4 3 In direct drive LED mode this pin indicates 100 Mbps link up or down In combined LED mode the output from LED_LINK10 LED_LINK100 and LED_LINK1000 must be read together to determine link and speed status L...

Page 24: ...ex collision modes The LED_DUPLEX pin may be pro grammed to Mode 1 or Mode 2 by setting register bit 24 2 Mode 1 Low Full duplex High Half duplex Blink Collision Mode 2 Low Full duplex High Half duplex Mode 3 Low Fiber Link up High Fiber Link down LED_DUPLEX is a multi function pin used to configure the 88E1111 device at the de assertion of hardware reset Table 10 LED Interface Continued 117 TFBGA...

Page 25: ...k Receiving LED_RX is a multi function pin used to con figure the 88E1111 device at the de asser tion of hardware reset D9 68 91 LED_TX O mA Parallel LED Transmit Activity or RX TX Activity Link modes LED_TX may be pro grammed to Mode 1 or Mode 2 by setting register bit 24 0 Mode 1 Low Transmitting High Not transmitting Mode 2 Low Link up High Link down Blink Transmitting or receiving LED_TX is a ...

Page 26: ...or L8 46 69 TMS I PU Boundary scan test mode select input TMS contains an internal 150 kohm pull up resistor L9 49 70 TCK I PU Boundary scan test clock input TCK contains an internal 150 kohm pull up resistor M9 47 68 TRSTn I PU Boundary scan test reset input Active low TRSTn contains an internal 150 kohm pull up resistor as per the 1149 1 specification After power up the JTAG state machine should...

Page 27: ...For the Two Wire Serial Interface TWSI device address the lower 5 bits which are PHYADR 4 0 are latched during hardware reset and the device address bits 6 5 are fixed at 10 E9 64 87 CONFIG 1 I CONFIG 1 pin configures PHY_ADR 4 3 and ENA_PAUSE options Each LED pin is hardwired to a constant value The values associated to the CON FIG 1 pin are latched at the de assertion of hardware reset CONFIG 1 ...

Page 28: ...G9 59 80 CONFIG 5 I CONFIG 5 pin configures DIS_FC DIS_SLEEP and HWCFG_MODE 3 options G8 58 79 CONFIG 6 I CONFIG 6 pin configures SEL_TWSI INT_POL and 75 50 OHM options H8 56 77 SEL_FREQ Frequency Selection for XTAL1 input NC Selects 25 MHz clock input Tied low Selects 125 MHz clock input Internally divided to 25 MHz SEL_FREQ is internally pulled up H9 55 76 XTAL1 I Reference Clock 25 MHz 50 ppm o...

Page 29: ...A I COMA disables all active circuitry to draw absolute minimum power The COMA power mode can be activated by asserting high on the COMA pin To deactivate the COMA power mode tie the COMA pin low Upon deactivating COMA mode the 88E1111 device will continue normal operation The COMA power mode cannot be enabled as long as hardware reset is enabled In COMA mode the PHY cannot wake up on its own by d...

Page 30: ...le 13 Test 117 TFBGA Pin 96 BCC Pin 128 PQFP Pin Pin Name Pin Type Description M5 M6 37 38 53 54 HSDAC HSDAC Analog PD Test pins These pins should be left floating but brought out for probing Table 14 Control and Reference 117 TFBGA Pin 96 BCC Pin 128 PQFP Pin Pin Name Pin Type Description M2 30 39 RSET Analog I Constant voltage reference External 5 0 kohm 1 resistor connection to VSS required for...

Page 31: ... 35 36 40 45 78 44 49 52 59 64 104 AVDD Power Analog Power 2 5V C6 C7 D7 E3 E7 F3 J3 J7 1 6 10 15 57 62 67 71 85 2 6 12 17 23 27 78 85 90 96 117 118 DVDD Power Digital Power 1 0V Instead of 1 0V 1 2V can be used B9 F7 J8 52 66 72 73 89 97 VDDOH Power 2 5V Power Supply for LED and CONFIG pins K9 L2 26 48 34 71 VDDOX Power 2 5V Supply for the MDC MDIO INTn 125CLK RESETn JTAG pin Power B4 C2 K1 5 21 ...

Page 32: ...G4 G5 G6 H4 H5 H6 J4 J5 J6 K4 K5 K6 L5 L6 0 1 9 15 21 22 38 40 43 45 48 51 55 58 60 63 65 66 83 84 93 94 101 102 103 106 108 111 116 119 127 VSS GND Global ground H7 53 74 VSSC GND Ground reference for XTAL1 and XTAL2 pins This pin must be connected to the ground G1 K7 13 51 50 NC NC No connect Do not connect these pins to anything Table 15 Power Ground Continued 117 TFBGA Pin 96 BCC Pin 128 PQFP ...

Page 33: ...ive Low Low Low Low Tri state COL Tri state TBI mode input else active Tri state Tri state TBI mode input else low TBI mode input else low Tri state RX_CLK Tri state Active Reg 16 3 state 0 Low 1 Active Low Reg 16 3 state 0 Low 1 Active Reg 16 3 state 0 Low 0 Static but can be either high or low Tri state S_CLK S_OUT Active Active Tri state Tri state Reg 16 3 state 0 Tri state 1 Active Tri state A...

Page 34: ...M3 AVDD D9 LED_TX M4 AVDD L3 MDC M7 AVDD N2 MDI 0 M8 AVDD N1 MDI 0 N5 AVDD N4 MDI 1 B6 COL N3 MDI 1 L4 COMA N7 MDI 2 D8 CONFIG 0 N6 MDI 2 E9 CONFIG 1 N9 MDI 3 F8 CONFIG 2 N8 MDI 3 G7 CONFIG 3 M1 MDIO F9 CONFIG 4 G1 NC G9 CONFIG 5 K7 NC G8 CONFIG 6 K3 RESETn B5 CRS M2 RSET C6 DVDD B2 RXD0 C7 DVDD D3 RXD1 D7 DVDD C3 RXD2 E3 DVDD B3 RXD3 E7 DVDD C4 RXD4 F3 DVDD A1 RXD5 J3 DVDD A2 RXD6 J7 DVDD C5 RXD7...

Page 35: ...TCK E4 VSS L7 TDI E5 VSS K8 TDO E6 VSS L8 TMS F4 VSS M9 TRSTn F5 VSS F1 TXD0 F6 VSS G2 TXD1 G4 VSS G3 TXD2 G5 VSS H2 TXD3 G6 VSS H1 TXD4 H4 VSS H3 TXD5 H5 VSS J1 TXD6 H6 VSS J2 TXD7 J4 VSS D1 TX_CLK J5 VSS E1 TX_EN J6 VSS F2 TX_ER K4 VSS B4 VDDO K5 VSS C2 VDDO K6 VSS K1 VDDO L5 VSS B9 VDDOH L6 VSS F7 VDDOH H7 VSSC J8 VDDOH H9 XTAL1 K9 VDDOX J9 XTAL2 L2 VDDOX 1 6 117 Pin TFBGA Pin Assignment List A...

Page 36: ...K1000 35 AVDD 69 LED_RX 36 AVDD 68 LED_TX 40 AVDD 25 MDC 45 AVDD 31 MDI 0 78 AVDD 29 MDI 0 83 COL 34 MDI 1 27 COMA 33 MDI 1 65 CONFIG 0 41 MDI 2 64 CONFIG 1 39 MDI 2 63 CONFIG 2 43 MDI 3 61 CONFIG 3 42 MDI 3 60 CONFIG 4 24 MDIO 59 CONFIG 5 13 NC 58 CONFIG 6 51 NC 84 CRS 28 RESETn 1 DVDD 30 RSET 6 DVDD 95 RXD0 10 DVDD 92 RXD1 15 DVDD 93 RXD2 57 DVDD 91 RXD3 62 DVDD 90 RXD4 67 DVDD 89 RXD5 71 DVDD 8...

Page 37: ...l by Signal Name 82 S_IN 4 TX_CLK 75 S_OUT 9 TX_EN 77 S_OUT 7 TX_ER 56 SEL_FREQ 5 VDDO 49 TCK 21 VDDO 44 TDI 88 VDDO 50 TDO 96 VDDO 46 TMS 52 VDDOH 47 TRSTn 66 VDDOH 11 TXD0 72 VDDOH 12 TXD1 26 VDDOX 14 TXD2 48 VDDOX 16 TXD3 0 VSS 17 TXD4 53 VSSC 18 TXD5 55 XTAL1 19 TXD6 54 XTAL2 20 TXD7 1 7 96 Pin BCC Pin Assignment List Alphabetical by Signal Name Continued Pin Pin Name Pin Pin Name ...

Page 38: ...00 LED_LINK10 52 AVDD 99 LED_LINK100 59 AVDD 98 LED_LINK1000 64 AVDD 92 LED_RX 104 AVDD 91 LED_TX 114 COL 35 MDC 37 COMA 41 MDI 0 88 CONFIG 0 42 MDI 0 87 CONFIG 1 46 MDI 1 86 CONFIG 2 47 MDI 1 82 CONFIG 3 56 MDI 2 81 CONFIG 4 57 MDI 2 80 CONFIG 5 61 MDI 3 79 CONFIG 6 62 MDI 3 115 CRS 33 MDIO 2 DVDD 50 NC 6 DVDD 36 RESETn 12 DVDD 39 RSET 17 DVDD 7 RX_CLK 23 DVDD 4 RX_DV 27 DVDD 8 RX_ER 78 DVDD 3 RX...

Page 39: ...70 TCK 43 VSS 67 TDI 45 VSS 72 TDO 48 VSS 69 TMS 51 VSS 68 TRSTn 55 VSS 10 TX_CLK 58 VSS 16 TX_EN 60 VSS 13 TX_ER 63 VSS 18 TXD0 65 VSS 19 TXD1 66 VSS 20 TXD2 83 VSS 24 TXD3 84 VSS 25 TXD4 93 VSS 26 TXD5 94 VSS 28 TXD6 101 VSS 29 TXD7 102 VSS 5 VDDO 103 VSS 11 VDDO 106 VSS 30 VDDO 108 VSS 122 VDDO 111 VSS 73 VDDOH 116 VSS 89 VDDOH 119 VSS 97 VDDOH 127 VSS 34 VDDOX 74 VSSC 71 VDDOX 76 XTAL1 1 VSS 7...

Page 40: ...Ultra Gigabit Ethernet Transceiver Doc No MV S105540 00 Rev Copyright 2009 Marvell Page 40 Document Classification Proprietary Information March 4 2009 Advance Section 2 Package Mechanical Dimensions 2 1 117 pin TFBGA Package All dimensions in mm ...

Page 41: ...s in mm Symbol MIN NOM MAX A 1 54 A1 0 40 0 50 0 60 A2 0 84 0 89 0 94 c 0 32 0 36 0 40 D 9 90 10 00 10 10 E 13 90 14 00 14 10 D1 8 00 E1 12 00 e 1 00 b 0 50 0 60 0 70 aaa 0 20 bbb 0 25 ccc 0 35 ddd 0 15 MD ME NOTE 1 CONTROLLING DIMENSION MILLIMETER 2 PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS 3 DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMET...

Page 42: ...rvell Page 42 Document Classification Proprietary Information March 4 2009 Advance 2 2 96 pin BCC Package Top View 9 00 0 10 Z Y TOP VIEW 0 15 0 670 0 025 0 80 MAX 0 075 0 025 PIN 1 CORNER X 9 00 0 10 0 20 0 05 1 3 50 51 71 73 24 95 96 74 75 27 49 47 25 23 0 30 0 05 DETAIL A 1X 0 08 Z C0 2 0 08 Z X Y 0 400 0 05 X Y M M Z Z ...

Page 43: ...ge 43 Package Mechanical Dimensions 96 Pin BCC Package Bottom View 2 3 96 Pin BCC Package Bottom View 0 40 0 05 CL PKG A PIN 1 CORNER BOTTOM VIEW 7 200 7 00 8 20 9 00 0 2 0 2 B 4 100 0 600 TYP 9 00 8 20 4 800 7 20 5 800 CL PKG 4 100 0 600 TYP 3 50 0 60 0 10 0 60 0 10 3 50 DETAIL B 95X 0 30 0 05 Y X Z 0 08 Y X Z 0 08 M M ...

Page 44: ... MV S105540 00 Rev Copyright 2009 Marvell Page 44 Document Classification Proprietary Information March 4 2009 Advance 2 4 128 Pin PQFP Package 0 5 Basic 0 25 min 1 6 Nominal 38 39 1 128 64 65 102 103 PIN1 INDICATOR 23 20 0 20 20 00 0 10 14 00 0 10 17 20 0 20 0 22 0 05 0 88 0 15 3 40 Max ...

Page 45: ...TFBGA Industrial 88E1111 XX BAB I000 88E1111 96 pin BCC Commercial 88E1111 XX CAA C000 88E1111 96 pin BCC Industrial 88E1111 XX CAA I000 88E1111 128 pin PQFP Commercial 88E1111 XX RCJ C000 Table 18 88E1111 Part Order Options RoHS 6 6 Compliant Package Package Type Part Order Number 88E1111 117 pin TFBGA Commercial 88E1111 XX BAB1C000 88E1111 117 pin TFBGA Industrial 88E1111 XX BAB1I000 88E1111 96 ...

Page 46: ...rking and Pin 1 Location 88E1111 BAB Lot Number YYWW xx Country Country of origin Contained in the mold ID or marked as the last line on the package Pin 1 location Note The above example is not drawn to scale Location of markings is approximate Logo Part number package code environmental code Environmental Code No code RoHS 5 6 1 RoHS 6 6 Date code custom code assembly plant code YYWW Date code xx...

Page 47: ... Lot Number YYWW xx Country Country of origin Contained in the mold ID or marked as the last line on the package Pin 1 location Note The above example is not drawn to scale Location of markings is approximate Part number package code environmental code Environmental Code No code RoHS 5 6 1 RoHS 6 6 Date code custom code assembly plant code YYWW Date code xx Custom code Assembly location code Logo ...

Page 48: ...ompliant package Figure 10 88E1111 128 pin PQFP Commercial RoHS 5 6 Compliant Package Marking and Pin 1 Location 88E1111 RCJ Lot Number YYWW xx Country Country of origin Contained in the mold ID or marked as the last line on the package Pin 1 location Note The above example is not drawn to scale Location of markings is approximate Part number package code environmental code Environmental Code No c...

Page 49: ...d Pin 1 Location 88E1111 BAB1 Lot Number YYWW xx Country Country of origin Contained in the mold ID or marked as the last line on the package Pin 1 location Note The above example is not drawn to scale Location of markings is approximate Logo Part number package code environmental code Environmental Code No code RoHS 5 6 1 RoHS 6 6 Date code custom code assembly plant code YYWW Date code xx Custom...

Page 50: ...88E1111 CAA1 Lot Number YYWW xx Country Country of origin Contained in the mold ID or marked as the last line on the package Note The above example is not drawn to scale Location of markings is approximate Pin 1 location Logo Part number package code environmental code Environmental Code No code RoHS 5 6 1 RoHS 6 6 Date code custom code assembly plant code YYWW Date code xx Custom code Assembly lo...

Page 51: ...ackage Figure 15 88E1111 128 pin PQFP Commercial RoHS 6 6 Compliant Package Marking and Pin 1 Location 88E1111 RCJ1 Lot Number YYWW xx Country Country of origin Contained in the mold ID or marked as the last line on the package Note The above example is not drawn to scale Location of markings is approximate Pin 1 location Logo Part number package code environmental code Environmental Code No code ...

Page 52: ...Marvell Moving Forward Faster Marvell Semiconductor Inc 5488 Marvell Lane Santa Clara CA 95054 USA Tel 1 408 222 2500 Fax 1 408 752 9028 www marvell com Back Cover ...

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