56
LC89057W
No. Port name
I/O Description
1 RXOUT
O Data Output
2 RX0
I Digital data Input (TTL)
3 RX1
I Digital data Input (Coaxial)
4 RX2
I Digital data Input (TTL)
5 RX3
I Digital data Input (TTL)
6 DGND
Digital GND
7 DVDD
Digital VDD
8 RX4
I Digital data Input (TTL)
9 RX5/VI
I Digital data Input (TTL)
10 RX6/UI
I Digital data Input (TTL)
11 DVDD
Digital GND for PLL
12 DGND
Digital VDD for PLL
13 LPF
O Loop filter for PLL
14 AVDD
Analog VDD for PLL
15 AGND
Analog GND for PLL
16 RMCK
O System clock Output for R (256fs, 512fs, XIN, VCO)
17 RBCK
O/I Bit clock Output for R (64fs)
18 DGND
Digital GND
19 DVDD
Digital VDD
20 RLRCK
O/I LR clock Input/Output for R
21 RDATA
O Serial Audio data Input
22 SBCK
O Bit clock Output for S (32fs, 64fs, 128fs)
23 SLRCK
O LR clock Output for S (fs/2, fs, 2fs)
24 SDIN
I Serial Audio data Input
25 DGND
Digital GND
26 DVDD
Digital VDD
27 XMCK
O Oscillation amplifier
28 XOUT
O XOUT
29 XIN
I XIN or External clock Input (24.576MHz or 12.288MHz)
30 DVDD
Digital VDD
31 DGND
Digital GND
32 EMPHA/UO
I/O Emphasis Information / U data Output / Set for chip address
33 AUDIO/VO
I/O Detected non-PCM / V flag Output / Set for chip address
34 CKST
I/O Clock timing Output / Switch to master or slave for demodulation
35 INT
I/O Interrupt Output / Switch to Modulation or general-purpose I/O
36 RERR
O Error Output (PLL lock, data error)
37 DO
O IF, Read out data Output
38 DI
I IF, Write data Input
39 CE
I IF, Chip enable Input
40 CL
I IF, Clock Input
41 XMODE
I System reset Input
42 DGND
Digital GND
43 DVDD
Digital VDD
44 TMCK/PIO0
I/O 256fs system-clock Input for modulation / General-purpose I/O input/output
45 TBCK/PIO1
I/O 64fs bit-clock Input for modulation / General-purpose I/O input/output
46 TLRCK/PIO2
I/O Fs clock Input for modulation / General-purpose I/O input/output
47 TDATA/PIO3
I/O Serial audio data for modulation / General-purpose I/O input/output
48 TXO/PIOEN
O/I Modulation data Output / General-purpose I/O enable input
RX6/UI
10
Microcontroller
I/F
CL
40
CE
39
DI
38
Selector
RX1
3
Input
RX0
2
RX2
4
RX3
5
RX4
8
RX5/VI
9
Demodulation
&
Lock detect
PLL
RDATA
21
Clock
Selector
C bit , Ubit
INT
35
EMPHA/UO
32
AUDIO
33
RERR
36
XIN
28
Modulation
RXOUT
1
XMODE
41
XOUT
29
TMCK/PIO0
44
TBCK/PIO1
45
TLRCK/PIO2
46
TDATA/PIO3
47
TXO/PIOEN
48
16
17
20
22
23
RMCK
RBCK
RLRCK
SBCK
SLRCK
DO
37
or
Parallel Port
1/N
LPF
13
27
34
24
SDIN
Data
Selector
XMCK
CKST
/VO
21
RDATA
22
SBCK
23
SLRCK
24
SDIN
37
DO
38
DI
39
CE
RX0
40
CL
41
XMODE
42
43
DVDD
44
TXO/PIOEN
45
TMCK/PIO0
RX3
RX1
DGND
DVDD
DVDD
RX6/UI
12
17
RBCK
18
DGND
19
DVDD
20
RLRCK
46
TBCK/PIO1
47
48
DGND
14
15
16
13
LPF
11
10
9
8
7
6
5
4
3
2
1
35
36
33
34
31
32
29
30
27
28
25
26
LC89057W-VF4-E
LC89057W-VF4-E
DGND
RXOUT
RX2
RX4
RX5/VI
AVDD
AGND
RMCK
TLRCK/PIO2
TDATA/PIO3
DGND
DVDD
XMCK
XOUT
XIN
DVDD
DGND
EMPHA/UO
AUDIO
CKST
INT
RERR
*
*
*
*
*
*
/V
O
IC13 : LC89057W
Summary of Contents for SR-3001
Page 22: ...22 21 8 BLOCK DIAGRAM 07 2 4 07 054 07 6 07 45 2 5 0 4 07 054 07 03 9 32 9 ...
Page 24: ...26 25 2 0 4 07 4 054 07 2 054 07 INPUT PWB 2 3 ...
Page 25: ...27 28 4 07 4 2 4 07 4 6 07 4 0 4 07 50 4 INPUT PWB 3 3 ...
Page 28: ...34 33 4 07 4 07 2 0 7 2 42 3 07 2 054 07 ENCORDER PWB FRONT PWB H P PWB PUSH SW PWB TACT PWB ...