163
LAN8700 (HDMI : U4202)
LAN8700 Block Diagram
nINT/TX_ER/TXD4
MDC
CRS/PHYAD4
MDIO
nRST
TX_EN
VDD_CORE
VDD33
LI
NK
/P
HYAD1
A
C
T
IV
IT
Y
/PH
YAD2
FDUPL
E
X
/PHYAD3
XTAL
2
CLKIN
/X
TAL1
RXD3
/nIN
TSEL
RXD1
/M
ODE1
RXD2
/M
ODE2
TXD3
RX_CLK/REGOFF
TX_CLK
RX_ER/RXD4
VDDIO
TXD1
TXD0
TXD2
COL/
RMII
/CRS
_DV
TXP
RX
N
VD
DA
3.3
E
XR
ES1
VD
DA3.3
RX
P
VD
DA3.3
USB3300
Hi-Speed USB2
ULPI PHY
32 Pin QFN
1
2
3
4
5
6
7
8
LAN8700/LAN8700I
MII/RMII Ethernet PHY
36 Pin QFN
GND FLAG
10
11
12
13
14
15
16
24
23
22
21
20
19
32
31
30
29
28
SPEED100/PHYAD0
V
D
_
X
R
9
RXD0
/M
ODE0
17
TXN
18
27
26
25
36
35
34
33
10M Rx
Logic
100M Rx
Logic
DSP System:
Clock
Data Recovery
Equalizer
Analog-to-
Digital
100M PLL
Squelch &
Filters
10M PLL
Receive Section
Central
Bias
HP Auto-MDIX
Management
Control
SMI
RMII
/ MII Lo
gic
TXP / TXN
TXD[0..3]
TX_EN
TX_ER
TX_CLK
RXD[0..3]
RX_DV
RX_ER
RX_CLK
CRS
L/CRS_DV
MDC
MDIO
SPEED100
LINK
ACTIVITY
FDUPLEX
LED Circuitry
MODE Control
nINT
nRST
RXP / RXN
10M Tx
Logic
10M
Transmitter
100M Tx
Logic
100M
Transmitter
Transmit Section
PLL
XTAL1
XTAL2
MODE0
MODE1
MODE2
PHY
Address
Latches
PHYAD[0..4]
Auto-
Negotiation
Interrupt
Generator
MII
MDIX
Control
Summary of Contents for AV7005/N1B
Page 62: ...62 Personal notes ...
Page 64: ...64 BLOCK DIAGRAM ...
Page 139: ...139 R5F3650KNFB HDMI U5500 ...
Page 146: ...146 IS42S32200E6TL HDMI U1602 IS42S32200E6TL Block diagram ...
Page 155: ...155 AK4424ET HDMI U3800 U3801 AK4424ET Block Diagram ...
Page 156: ...156 AK5358BET HDMI U3802 AK5358BET Pin Function ...
Page 160: ...160 HY27UF081G2A TPCB Block Diagram ...
Page 170: ...170 2 FL DISPLAY FLD 19 ST 02GINK FRONT Z1001 PIN CONNECTION GRID ASSIGNMENT ...
Page 171: ...171 ANODE CONNECTION ...
Page 172: ...172 VFD GP1261AI FRONT Z1002 PIN CONNECTION PATTERN DETAIL ...