MAI Basic Four 2000 Series Page 43 Service Manual Download

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BFISD 8079

Figure 2-7. Location of Switch on Magnetic Cartridge Streamer Controller PCBA

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Summary of Contents for 2000 Series

Page 1: ...Basic Four Series 2000 Desktop Computer System BFISD8079A Service Manual...

Page 2: ......

Page 3: ...4 4 Way Controller PCBA 2 17 2 5 Installing the Local Area Network LAN 2 20 2 5 1 Installing the LANG Board 2 20 2 5 2 Installing the Tap Box 2 24 2 5 3 Installing the Repeater 2 25 2 5 3 1 Connecting...

Page 4: ...rd Selection 3 26 3 2 14 2 Memory Array Bus Multiplexing 3 26 3 2 15 Dynamic Memory Support 3 27 3 2 15 1 Memory Timing 3 28 3 2 15 2 Row Address Strobe 3 28 3 2 15 3 Column Address Strobes 3 28 3 2 1...

Page 5: ...d CMB 5 1 5 3 Replacing the Base Unit Power Supply 5 9 5 4 Replacing the Memory Array Modules 5 11 5 5 Replacing the 4 Way Controller Boards 5 14 5 6 Replacing the Winchester Drive Controller WDC Boar...

Page 6: ...cifications 7 17 7 2 Installation and Maintenance 7 20 7 2 2 Equipment Placement 7 20 7 2 3 Electrical Installation 7 20 7 2 4 Adjustment Procedures 7 20 7 2 4 1 Index Burst Position Adjustment 7 21 7...

Page 7: ...5 4 Preamplifier PCBA Removal and Replacement 8 52 8 6 Parts List 8 52 SECTION IX 50 MEGABYTE WINCHESTER DRIVE SYSTEM 9 1 Introduction 9 1 9 1 1 General Description 9 1 9 1 2 Functional Concepts 9 2...

Page 8: ......

Page 9: ...plified Block Diagram Central Microprocessor Board 3 2 3 2 Timing Diagram PDTACK and Bus Error Generation 3 19 3 3 Address Space Decoding Logic 3 23 3 4 Timing Relationships for the Signals of a Dynam...

Page 10: ...Diagram 7 4 7 5 Stepper Motor Control Circuit Block Diagram 7 5 7 6 Stepper Motor Timing Diagram 48 TPI 7 5 7 7 Stepper Motor Timing Diagram 96 TPI 7 5 7 8 Stepper Motor Phase Transfer Chart 7 6 7 9...

Page 11: ...9 8 8 Data Transfer to Host Timing 8 20 8 9 Data Transfer from Host Timing 8 21 8 10 Device Control Block DCB Format 8 22 8 11 Completion Status Bytes 8 23 8 12 Winchester Drive Assembly 8 49 8 13 Hea...

Page 12: ......

Page 13: ...ls 3 52 3 9 Centronics Protocol 3 53 3 10 Command List WD1793 Floppy Disk Controller Chip 3 65 3 11 State Machine States 3 69 5 1 CMB Jumper Configuration 5 8 5 2 Memory Array Module Address Switch Se...

Page 14: ...er Connector J3 Pin Assignments 9 9 9 5 Power Requirements 9 13 9 6 Head Select Decode Matrix 9 17 9 7 SASI Bus Status Signals 9 20 9 8 Summary of SASI Bus Status Signals 9 20 9 9 Controller Host Hand...

Page 15: ...Megabyte Winchester Drive System Section X Schematics NOTICE MAI Basic Four equipment is designed to meet the safety requirements of Underwriters Laboratories UL and the emission requirements of the F...

Page 16: ...BFISD 8079 Figure 1 1 Model 4108 Base Unit xvi...

Page 17: ...t the Central Microprocessor Board Residing on the Central Microprocessor Board are two serial ports a parallel port and a floppy disk controller All subunits either are located on or plug into the Ce...

Page 18: ...e Other features include three major data sizes byte word long word supervisor and user states and many flexible addressing options The central processor sec tion also includes the local I O bus and t...

Page 19: ...s The Memory Array boards contain the active elements i e RAM chips and signal buffers that make up the main system memory The array itself consists of industry standard 64K X 1 dynamic RAM chips Each...

Page 20: ...RS 232C interface via 9 pin D connectors located on the 4 Way Controller board Modem capabilities are provided for remote terminal support The 4 Way Controller also supports eight bit character trans...

Page 21: ...er and workstations Up to 63 subsystems nodes can be connected via the LAN Each subsystem follows the Carrier Sense Multiple Access Collision Avoidance CSMA CA protocol when it is accessing the networ...

Page 22: ...9A 12 VDC nominal 0 4A 12 VDC nominal ENVIRONMENTAL Operating Temperature 50 F to 98 4 F 10 C to 38 C Relative Humidity 20 to 80 non condensing Altitude Sea level to 10 000 feet Storage Temperature 5...

Page 23: ...ives Serial I O Channels Two to sixteen asynchronous bidirec tional EIA RS 232C ports and one 2 wire local area network LAN port Parallel I O Channels One 8 bit output channel for connection to any pl...

Page 24: ......

Page 25: ...om the main chassis causing the chassis to fall Lift the Base Unit from the carton as follows grasp the Base Unit at opposite ends by wrapping your fingers around the bottom corners Make sure your fin...

Page 26: ...ures in REMOVAL REPLACEMENT Section V in this manual For convenience PCBA switch settings jumper placements and cable connections are also included in this section in paragraph 2 4 3 Place the Base Un...

Page 27: ...Base Unit requires a 6A rating for 100 120 VAC and a 3A rating for 220 240 VAC 10 Plug in the power cables for both the Base Unit and the terminal and turn on the terminal 11 Turn on the Base Unit dep...

Page 28: ...57 43 PM 10 03 84 Update clock hhmmssxx mtnddyy Wed Oct 3 1984 12 57 45 single user mode ADMIN 14 Shut down the system as follows a Press CTRL D b Type shutdown CR c Wait for the prompt and then turn...

Page 29: ...the system is equipped with the Magnetic Cartridge Streamer MCS unit plug the PB end of the MCS cable into the back of the MCS unit Plug the PA end into the connector on the MCS Controller board at th...

Page 30: ...each periheral device in the system Note Configuration changes will not occur until the operating system is re booted 23 Shut down the system and re boot 24 Press CTRL D 25 Type in multi and press CR...

Page 31: ...in shutdown 0 b Press CTRL D c Type in shutdown d Wait for the prompt and then turn OFF the Base Unit power by depressing the 0 side of the power switch at the rear of the Base Unit 31 Replace the Ba...

Page 32: ...BFISD 8079 Figure 2 2 Location of Jumpers on Central Microprocessor Board 2 8...

Page 33: ...BFISD 8079 Figure 2 3 Central Microprocessor Board Cable Part Numbers 2 9...

Page 34: ...2K x 8 2 and 3 2732 4K x 8 1 and 2 Connect jumper R This jumper when disconnected disables the memory refresh circuitry thereby allowing easier debugging of memory and bus arbitration cir cuits Normal...

Page 35: ...and 16 pin 3 15 and 16 pin 2 15 and 16 pin 2 DCDB 17 and 18 pin 8 17 and 18 pin 8 TRXCB 10 and 20 pin 15 19 and 20 pin 15 23 and 24 23 and 24 Jumper H Jumper H DCDB 1 and 2 1 and 2 Jumper K Jumper K J...

Page 36: ...0 microprocessor at one time without the processor having to read from the disk sector by sector RAM SIZE JUMPER D 2K x 8 2 and 3 8K x 8 1 and 2 Connect Jumper E The floppy disk controller located on...

Page 37: ...and 9 Serial Port B CTS B 8 and 10 Serial Port B RTSB B 13 and 15 Serial Port B RXDB B 14 and 16 Serial Port B TXDB C None EPROM Size Select 2732 2764 D 2 and 3 Floppy Sector Buffer Size Select 2K x...

Page 38: ...CARE ON OFF OFF 1024 to 1280 ON ON DON T CARE OFF ON ON 1280 to 1536 ON ON DON T CARE OFF ON OFF Note OFF OPEN and ON CLOSED 2 4 3 Winchester Disk Single Board Controller Connect the appropriate jumpe...

Page 39: ...BFISD 8079 Figure 2 4 Location of Address Switches on Memory Array Module 2 15...

Page 40: ...BFISD 8079 Figure 2 5 Location of Jumpers on Single Board Winchester Disk Controller 2 16...

Page 41: ...001 PCB detail 904943 001 current production future production TERMINAL PRINTER MODEM TERMINAL PRINTER MODEM 1 to 7 1 to 2 1 to 3 1 to 2 2 to 8 3 to 4 2 to 4 3 to 4 3 to 4 7 to 8 9 to 11 9 to 10 9 to...

Page 42: ...BFISD 8079 Figure 2 6 Location of Switches on 4 Way Controller PCBA 2 18...

Page 43: ...BFISD 8079 Figure 2 7 Location of Switch on Magnetic Cartridge Streamer Controller PCBA 2 19...

Page 44: ...st 1 000 feet and an additional repeater when there are more than 32 systems on the network 63 systems maximum The network cable is twin lead shielded or unshielded Local electrical and fire regulatio...

Page 45: ...BFISD 8079 Figure 2 8 Location of Switches and Cable Information for LANC PCBA 2 21...

Page 46: ...st address is 000001 and the 63rd address is 111111 all switches off Note 000000 is illegal Switch S1 is the Bias switch and normally is set to the on position however one station must have this switc...

Page 47: ...k Controller PCBA into the CMB or into the PCBA at the top of the stack at the rear right hand corner of the CMB Line up the connectors then press down firmly to connect the board being very careful n...

Page 48: ...where along the network cable with no minimum or maximum distance between them The diagram in figure 2 9 shows the layout of the Tap Box with labels added for reference Each Tap Box contains five pair...

Page 49: ...ghten the screw 9 Insert the ground wire into screw terminal B3 and tighten the screw 10 Remove three cutouts from the Tap Box and install the grommet for each cable into a cutout hole 11 If the Tap B...

Page 50: ...the two screw connector terminal strips The terminal strip at the top of the box is for connecting the power tranformer The terminal strip at the bottom of the printed circuit board is for connecting...

Page 51: ...y to the right of the red wire just connected and tighten the screw 7 Insert the ground wires from both segments into the adjoining drain connectors and tighten the screws 8 If a network branch is des...

Page 52: ...tighten the screw 5 Insert the red wire at the other end of the power cable into the con nector labeled on the power transformer and tighten the screw 6 Insert the remaining black wire into the conne...

Page 53: ...uld the power be turned off when diskettes are in the drives Turning the power on and off with diskettes in the drives can result in damage to the diskettes and in loss of data A few simple precaution...

Page 54: ...a can be recorded One use of this feature is to protect backup copies of soft ware or data It is a good idea to write protect a master diskette and its backup copy so that neither can be inadvertently...

Page 55: ...l I O input output These are linked primarily by the system bus structure Figure 3 1 is a block diagram of the CMB logic highlighting the flow of addresses and data The central processor section is ba...

Page 56: ...BFISD 8079 TBD Figure 3 1 Simplified Block Diagram Central Microprocessor Board 3 2...

Page 57: ...of operation user mode and supervisor mode A bit in the 68010 status register indicates the current mode The 68010 allows privileged instructions to be executed only in the supervisor mode If an atte...

Page 58: ...peripheral device controllers on the system I O bus For local use the non decoded function code CFC2 is buffered in a 74LS04 in verter 7R to become CFC2 A and CFC2 When these signals are asserted the...

Page 59: ...des the CMB status drivers and the CMB control register 3 2 4 1 CMB Status Drivers There are times when the diagnostic program requires a snapshot of the status of the Central Microprocessor Board The...

Page 60: ...Always low CD15 Always low The CMB control register cannot be read The various bit functions are shown in table 3 2 3 2 5 Main Memory Fault Detection Circuits Main memory fault protection is provided...

Page 61: ...ed in a register discussed in paragraph 3 2 5 1 to facilitate error logging and error recovery A more ob vious response however is the bus error trap generated by the parity check which discontinues u...

Page 62: ...74 transparent latch 3N and a 74LS240 inverter 3S The inputs to the parity error register include the following The four high order memory array address bits from the 68010 or from a peripheral device...

Page 63: ...I O in a computer system One is initiated by the processor program controlled and the other is initiated by the I O port interrupt driven The difference be tween the two is in the method used to deter...

Page 64: ...7 the CVPA CPU Valid Peripheral Address output of the data selector is low active for inter rupt levels 2 and 4 the CVPA output is active only when the AVTR Auto VecToR input from the system I O bus...

Page 65: ...RIACK provides the data bus direction control Like the data selector the decoder 10L is enabled when FDC7 Function DeCode 7 is active and indicates a 68010 interrupt acknowledge cycle is in process 3...

Page 66: ...a peripheral device controller when that controller has control of the system I O bus The CPU Lower and Upper Data Strobes CLDS and CUDS are ORed together by a 74S08 AND gate 7T to provide signal CDS...

Page 67: ...ct timing for the NVRAM A08 A is used for the A00 input to the NVRAM this accounts for the interlaced segments previously mentioned Also note that the NVRAM does not have A6 and A7 address bit inputs...

Page 68: ...Transfer ACKnowledge to be returned during every memory bus cycle This input indicates that the data transfer is completed When the 68010 recognizes the PDTACK signal during a READ cycle data is latch...

Page 69: ...er 680010 Printer device baud rate if applicable 680012 Download device type 680014 Download device unit number 680016 Download device baud rate 680018 Reserved 68001A Reserved 68001C Reserved 68001E...

Page 70: ...Controller NEC 4 Magnetic Cartridge Streamer Controller 5 Parallel I O PI T 6 Unit Number Serial Communications Controller 0 1 4 Way Controller 0 15 Floppy Disk Controller 0 1 Winchester Disk Control...

Page 71: ...ad Write R W signal is ANDed with UDS and LDS which prevents the shift register from being held reset for an additional clock cycle during the beginning of a normal 68010 WRITE cycle At the beginning...

Page 72: ...One NAND gate 7N does nothing A fourth NAND gate 7N enables the PDTACK signal from the floppy buffer memory This allows only 4 wait states during access of that memory instead of the 14 wait states re...

Page 73: ...begins 3 2 11 Bus Arbitration Logic All peripheral controllers that plug into the Central Microprocessor Board use direct memory access DMA techniques to transfer data to and from the system main mem...

Page 74: ...s request signal is buffered by a 74S244 tristate driver IE and sent to the 68010 At the time of the bus request signal the priority resolution cycle begins Bus access prioritization is done with the...

Page 75: ...inning device must wait until allthese conditions are met before it may assume control of the system I O bus When the conditions are met the device taking the bus leaves its priority number on the pri...

Page 76: ...X6 WRITE Parity data forced 2XXXX8 WRITE Inhibit serial port drivers 2XXXXA WRITE Turn on LED 2XXXXC WRITE Inhibit parity response 2XXXX2 READ Memory Parity Error Upper Register 2XXXX4 READ Memory Par...

Page 77: ...ng READ cycles only four outputs are active during WRITE cycles only and one output is active during both READ and WRITE cycles MDENB Except for the MDENB Memory Data ENBable line the output lines are...

Page 78: ...ower data strobes CLDS and CUDS from the 68010 The enable inputs of the WRITE cycle decoder also re quire an active WR WRite signal which is the buffered R W control signal from the 68010 3 2 12 3 Mem...

Page 79: ...RCE NVRAM READ WRITE 68XXXX NVRST NVRAM store 6AXXXX NVRRC NVRAM recall 6CXXXX 3 2 13 Byte Interface Control Logic An 8 bit wide local data bus is present on the Central Microprocessor Board All the l...

Page 80: ...memory timing circuit first asserts the row address strobe MRAS the CADSEL Column ADdress SELect strobe is low Refer to the CMB Logic Diagram sheets 37 and 38 This enables a 74S244 tristate driver IV...

Page 81: ...AM chip has been replaced by row and column selects These indicate which address is on the address lines when the chip is selected The low order address bits from the bus master become the row address...

Page 82: ...DL2 CMB Logic Diagram sheet 37 deter mines all the subsequent memory timing The Address Strobe AS comes from Central Microprocessor Board connector J02 pin A31 Either a system I O bus peripheral devi...

Page 83: ...BFISD 8079 TBD Figure 3 5 Simplified Block Diagram Dynamic Memory Support Subsystem 3 29...

Page 84: ...I O bus and when asserted low indicates that either the 68010 or an I O bus peripheral device controller is doing a write cycle Signal MDENB inactive deselects the memory by preventing the column addr...

Page 85: ...DRS REFresh ADdResS and the other counter is clocked by the overflow from the first counter With each tick of the refresh clock the counter advances and the controller generates a memory request at th...

Page 86: ...When the 68010 returns the BGNT A Bus GraNT signal and the current bus cycle is not an interrupt acknowledge cycle signal SRFSHFO is created in a 74LS260 NOR gate 7J SRFSHFO is latched by another of t...

Page 87: ...he necessary hardware for the implementation of the memory management scheme used by the operating system software The MMU hardware provides for the two cooperating memory management techniques known...

Page 88: ...o there is no point in wasting overhead storing it on the disk if an image of the segment already exists there The reporting of a segment having been written to is yet another function of the MMU hard...

Page 89: ...BFISD 8079 TBD Figure 3 8 Simplified Block Diagram Memory Management Unit 3 35...

Page 90: ...base address limit address and segment attribute registers described in subsequent paragraphs which are part of the MMU can be updated only in supervisor mode Also all DMA Direct Memory Access transf...

Page 91: ...segment registers is addressed by signals MFA1 MFA2 and MFA3 These come from a 74S157 l of 2 data selector 3T Refer to the CMB Logic Diagram sheet 32 Address bits A01 A A02 A and A03 A are selected wh...

Page 92: ...format is as follows 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 0 0 0 A20 A19 A18 A17 A16 A15 A14 A13 A12 All A10 A09 In a 68010 memory cycle the logical address from the 68010 is compared wit...

Page 93: ...e status word when a logical 1 means the following BIT EXPLANATION D01 A segment has been written to not an error condition D02 A segment execute error has occurred error D03 A segment write error has...

Page 94: ...is asserted when a memory write cycle occurs during the user mode SEGWRT generates the Memory Management Write ERRor sig nal MMWERR MMWERR described in paragraph 3 2 16 8 This can occur only when the...

Page 95: ...DISable is provided to disable the MMU registers during bed of nails testing Refer to the CMB Logic Diagram sheet 30 When the input of the 74LS04 inverter 4V is pulled low by the tester RAMDIS goes h...

Page 96: ...BFISD 8079 TBD Figure 3 10 Simplified Block Diagram CMB Serial Ports 3 42...

Page 97: ...el device and each independent channel or port can handle 0 to 1M bits per second data transfer rates and full duplex operation A simplified block diagram of the 8530 chip is presented in figure 3 11...

Page 98: ...during the transmit cycle The benefit in this case stems from the elimination of idle time between character bytes on the serial output line The moment the final bit of a character byte leaves the ou...

Page 99: ...to inform the receiving serial port of the beginning and the end of that character It does this with start bits and stop bits When no data is being transmitted the data line carries a logic 1 level h...

Page 100: ...ines 21 signals and a 25 pin electrical connector for asynchronous serial data communication In order to accommodate terminals and serial printers in addition to modems the serial port circuitry in th...

Page 101: ...L PRINTER Name Jumper B Cable Jumper B Cable Jumper B Cable CTS 7 and 8 pin 5 7 and 9 pin 4 7 and 9 pin 4 DSR 3 and 4 pin 6 3 and 1 pin 20 3 and 1 pin 20 DTR 1 and 2 pin 20 2 and 4 pin 6 2 and 4 pin 6...

Page 102: ...een transferred between a shift register and a buffer register in the SCC chip This is so that a driver routine can either load a new byte into the transmit buffer or transfer the new byte in the rece...

Page 103: ...ow X Don t care The program now can read the status register in the SCC to determine whether the interrupt was due to the transmission or reception of data then the 68010 can move data to or from the...

Page 104: ...erator described in paragraph 3 2 10 1 The two signals are ANDed so that the PI T can start the strobes on a clean clock edge CST1F The internal registers of the PI T chip are addressed by address bit...

Page 105: ...parallel data output is asynchronous and the data transfer rate is deter mined by the transfer program which normally is interrupt driven The drivers and receivers in the parallel port circuitry are 7...

Page 106: ...e identifiers however are never rewritten during normal operation though the controller has the capability of writing those identifiers onto a blank disk ette when that diskette is being initialized f...

Page 107: ...acter or a function code has been accepted Data Bit 1 Sent by the Model 4108 Base Unit 1 Data Bit 2 Sent by the Model 4108 Base Unit 2 Data Bit 3 Sent by the Model 4108 Base Unit 3 Data Bit 4 Sent by...

Page 108: ...BFISD 8079 TBD Figure 3 12 Simplified Block Diagram CMB Floppy Disk Controller 3 54...

Page 109: ...nsas City Standard KSC for cassette recording The KSC en coding technique is shown in figure 3 13 A binary 0 is recorded as four full cycles of a 1200 Hz square wave A binary 1 is recorded as eight fu...

Page 110: ...y of the logic 1 cycle Therefore the logic 1 cycle has a transition in the middle of a clock cycle On the other hand the logic 0 cycle has no such transition A maximum data transfer rate is used in FM...

Page 111: ...ed data separators because the detector works with a phase locked loop to separate the composite clock and data signal into clock only and data only signals 3 2 19 3 MFM Data Separation Data separatio...

Page 112: ...ector logic of the phase locked loop by clocking a 74LS74 D flip flip 14X pin 3 to a cleared condition Before or after the one shot clears a clock pulse from the local oscillator will trigger another...

Page 113: ...d by the clock The delay is indicated by a low output from the NOR gate 14W pin 10 which allows the phase detector to continue working The delay also is represented by positive going pulses from one o...

Page 114: ...ion The pulse width of the PUMP UP and PUMP DOWN error signals is proportional to the required amount of frequency correction Each of these pulse trains looks like a pulse width modulated replica of t...

Page 115: ...trace shows five data pulses recorded on the diskette at the apparent positions indicated When the pulses are read back from the diskette they are shifted in time from their apparent recorded positio...

Page 116: ...n that byte and in turn to determine which bits will suffer from bit shifting For example if a data bit is a 0 and has a 1 bit on each side of it then the neighboring bits will be shifted toward the m...

Page 117: ...nsity mode in our system The chip controls head motion by issuing step pulses and head load commands to the drive Step pulses move the read write head arms from from track to track The head load comma...

Page 118: ...l byte is present The byte is in the data register in the chip and will be passed to the 68010 over the byte wide data bus Data to be written to the diskette flow from the 68010 to the controller chip...

Page 119: ...erate the appropriate signals at the controller chip pins labeled STEP and DIRECTION In addition to these arm control signals there are four output signals for writing data o WD Write Data o WGATE Wri...

Page 120: ...nal to count diskette revolutions and abort incomplete operations if they do not finish inside of the allotted number of revolutions Signal READY usually is connected the drive power or to a switch on...

Page 121: ...nsists of four cascaded 74LS393 4 bit counters UN and 12K Refer to the CMB Logic Diagram sheet 45 Signal INC BUFADR INCrement BUFfer ADdRess which is asserted at the end of every completed DMA state m...

Page 122: ...g edge of the K2MHZ clock Another output is both ORed and latched directly also on the falling edge of the K2MHZ clock Finally several of those flip flop outputs are used directly for chip control whi...

Page 123: ...buffer RAM enable signals BUFMEMWE and BUFMEMRE go low at the outputs of another 74LS157 US Refer to the CMB Logic Diagram sheet 43 State 4 Removes write enable BUFMEMWE releases State 5 Removes read...

Page 124: ...ding and g all commands to the floppy disk controller chip command register o The transfer of all status information from the floppy disk controller section to the 68010 These include a interrupt and...

Page 125: ...ansfer of sector data an appropriate signal is generated at the chip and may be used to interrupt the 68010 A 74LS51 combination gate 10W collects the two kinds of interrupts INTR A INTeRrupt and DRQ...

Page 126: ...utine At the same time that the priority number on the address bus was being decoded to produce CVPA a 74LS138 1 of 8 decoder 10L CMB Logic Diagram sheet 20 also decoded those address bits The output...

Page 127: ...2 SPECIAL TOOLS Maintenance procedures contained in this manual require no special tools or special test equipment 4 3 PREVENTIVE MAINTENANCE INCOMPLETE Preventive maintenance consists of performing r...

Page 128: ...ground wires and all connectors and PCBAs are seated properly 5 Check the ac line as a possible cause of problems i e sharp drops in voltage transients and poor grounds are common problems Check dc vo...

Page 129: ...the ribbon cable s going from the Winchester Drive s to the Winchester Drive Controller WDC PCBA located in the card cage at the rear right hand corner of the CMB Note two of the drive con nectors on...

Page 130: ...ng the Supply from the CMB unplugging the Supply from the CMB The Central Microprocessor Board now may be removed from the Base Unit bottom panel To install the replacement CMB proceed as follows refe...

Page 131: ...BFISD 8079 Figure 5 1 Location of Jumpers on Central Microprocessor Board 5 3...

Page 132: ...BFISD 8079 Figure 5 2 Central Microprocessor Board Cable Part Numbers 5 4...

Page 133: ...RINTER Name Jumper A Cable Jumper A Cable Jumper A Cable CTS 7 and 8 pin 5 7 and 9 pin 4 7 and 9 pin 4 DSRA 3 and 4 pin 6 1 and 3 pin 20 1 and 3 pin 20 DTR 1 and 2 pin 20 2 and 4 pin 6 2 and 4 pin 6 R...

Page 134: ...onously and asynchronously Jumper L connects the master clock to the Baud rate generator used for asynchronous input output Jum per M connects the synchronous clock to the port These clocks are discon...

Page 135: ...nd 4 19 Verify that jumper S is not connected This jumper is only to be used when calibrating the Western Digital data separator The jumper grounds the VFOE input to the WD1691 simulating a read condi...

Page 136: ...and 3 Floppy Sector Buffer Size Select 2K x 8 E 1 and 2 Floppy Data Separator Select Data E 7 and 8 Floppy Data Separator Select Clock F 1 and 2 Floppy Density Select G 15 and 16 Serial Port B RXDB G...

Page 137: ...the bot tom rear left hand corner of the drive chassis on the Master Electronics PCBA c Lower the back of the drive chassis so that it pushes back the two 2 plastic latches on the CMB at the bottom re...

Page 138: ...the Winchester Drive s to the Winchester Drive Controller WDC PCBA located in the card cage at the rear right hand corner of the OMB Note two of the drive con nectors on the WDC PCBA are situated sid...

Page 139: ...t the nearest 4 pin power plug to the connector located at the bottom rear left hand corner of the Winchester Drive s chassis 17 Turn the Base Unit power ON 18 Connect the positive test probe of a dig...

Page 140: ...m memory array PCBA from the CMB To install the replacement Memory Array PCBA s proceed as follows 4 Set the appropriate switches for the desired physical address of the Memory Array PCBA See table 5...

Page 141: ...BFISD 8079 Figure 5 3 Location of Address Switches on Memory Array Module 5 13...

Page 142: ...ve the cover 3 Unplug the WDC Bus Adapter PCBA and the WDC PCBA which carries the WDC PCBA as a single unit from the top of the stack This step may not be necessary refer to step 4 4 Unplug from the s...

Page 143: ...tail 904741 001 current production TERMINAL PRINTER MODEM 1 to 7 1 to 2 2 to 8 3 to 4 3 to 4 7 to 8 9 to 10 9 to 10 13 to 15 13 to 14 14 to 16 15 to 16 PCB detail 904943 001 future production TERMINAL...

Page 144: ...BFISD 8079 Figure 5 4 Location of Switches on 4 Way Controller PCBA 5 16...

Page 145: ...lied to the Base Unit 1 Shut down the system and turn the Base Unit power OFF 2 Insert a screwdriver or similar device into the slot at the bottom right hand side of the Base Unit cover and push in to...

Page 146: ...e WDC PCBA 10 Plug the 4 pin power connector coming from the WDC Bus Adapter PCBA into connector J3 at the front right hand corner of the WDC PCBA 11 Plug the ribbon cable s coming from the Winchester...

Page 147: ...BFISD 8079 Figure 5 5 Location of Jumpers on the Winchester Drive Controller PCBA 5 19...

Page 148: ...llowing steps 5 Set the appropriate switches on the MCSC PCBA for the correct bus arb itration number and mode according to the listing shown below See figure 5 6 for the location of the switches SWIT...

Page 149: ...BFISD 8079 Figure 5 6 Location of Switch on Magnetic Cartridge Streamer Controller PCBA 5 21...

Page 150: ...C Bus Adapter PCBA by releasing the re tainers on the 4 plastic standoffs at each corner of the WDC PCBA and lifting the WDC PCBA upward To install the replacement Winchester Drive Controller Bus Adap...

Page 151: ...disengage the the plastic latch Repeat with the left hand side and remove the cover 3 Unplug the WDC Bus Adapter PCBA and the WDC PCBA which carries the WDC PCBA as a single unit from the top of the s...

Page 152: ...BFISD 8079 LAN CONTROLLER LANC Figure 5 7 Location of Switches on Local Area Network Controller PCBA 5 24...

Page 153: ...rd has one unique address the first address is 000001 and the 63rd address is 111111 i e all switches turned off Note 000000 is illegal Switch S1 is the Bias switch and normally is set to the on posit...

Page 154: ...ver onto the Base Unit and allowing it to snap into place 9 Plug in all connections to the Base Unit including all previously at tached peripherals 5 10 REPLACING THE WINCHESTER DRIVE To replace the W...

Page 155: ...Pull the Drive slightly to the front of the CMB so that the flange at the bottom of the Drive chassis enters the slot in the Base Unit front panel 13 Connect the 4 pin power plug to the connector loca...

Page 156: ...he rear of the CMB so that the flange at the bottom front of the drive is out of the slot in the bottom pan el of the Base Unit 8 Unplug the ribbon cables from the CMB Note the two floppy drive connec...

Page 157: ...17 Reinstall the Memory Array PCBAs into the card cage at the front right hand corner of the CMB by plugging the bottom PCBA into the CMB The entire stack may be reinstalled as a unit 18 Replace the...

Page 158: ......

Page 159: ...th this manual 6 2 INDEX OF ASSEMBLIES The following is an index of the assemblies subassemblies covered in this section FIGURE TABLE TITLE PAGE 6 1 Central Microprocessor Board PCBA 6 2 3 6 2 Memory...

Page 160: ...BFISD 8079 Figure 6 1 CMB PCBA 6 2...

Page 161: ...onn D Fml Rt Ang PC MT Metal Face 37 Pos J13 300093 001 Conn DIN Male 3x32 0 025Sq 64 Pos A C Jl 2 3 300032 002 Conn Hdr 0 025Sq Dbl Row 100 6 Pos JMPA JMPB 2 REQD 300032 003 Conn Hdr 0 025Sq Dbl Row...

Page 162: ...Triple Input NAND 8S 101714 IC 74LS32 Quad 2 Input OR 12J 9V 4M 101715 IC 74S51 Dual 2 Wide 2 Input AND OR Inv 6M 7Y 101718 IC 74LS109 Dual J K Pos Edge Trig F F 10R 7S 8V 101719 IC 74LS138 3 8 Line...

Page 163: ...61129 001 IC 74S22 Dual 4 Input NAND OC 6Y 6Z 161133 001 IC 74LS148 8 3 Priority Encoder 3E 161141 001 IC 74LS153 Dual 4 1 Select MUX 2H 2J 9L 2W 161152 001 IC 74LS629 VCO 13Y 161155 001 IC 74S40 Dual...

Page 164: ...Resis R10 2F R23 10S 119000 005 Resis Ntwk DIP 10K Ohm 16 Pin 15 Resis 13N R24 119000 007 Resis Ntwk DIP 220 Ohm 16 Pin 15 Resis R26 14L 119001 004 Resis Ntwk DIP 10K Ohm 8 Pin 7 Resis R17 119004 004...

Page 165: ...BFISD 8079 THIS PAGE LEFT BLANK INTENTIONALLY 6 7...

Page 166: ...BFISD 8079 Figure 6 2 Memory Array 256K PCBA 6 8...

Page 167: ...Quad 2 Input Exclusive NOR U4P 161009 IC 74S240 Octal Buffer 3 State TTL U1L U3L U4L 161066 001 IC 74LS245 Octal Bus Receiver U1P U3P 161074 001 IC 74S244 Octal Buffer U1N U3M 161129 001 IC 74S22 Dua...

Page 168: ...BFISD 8079 Figure 6 3 WDC Bus Adapter PCBA 6 10...

Page 169: ...D 5D 101630 IC 74S112 Dual J K Edge Trig F F 3E 5F 101631 IC 74S138 Decoder DEMUX 2J 101633 IC SN74S157 Quad 2 1 Linedata Select MUX 3B 101637 IC SN74S260 Dual 5 Input Pos NOR 2E 101655 IC 74S02 Pos N...

Page 170: ...k DIP 1K Ohm 8 Pin 7 Resis Rl 2 Sockets 325005 011 Socket IC DIP 4 Leaf Cont Gold 20 Pos 4F 4E Switches 331005 002 Switch SPST DIP 8 Pos SW1 4B Miscellaneous 907634 001 Cable Assy DC Pwr WDC Bus Adapt...

Page 171: ...BFISD 8079 THIS PAGE LEFT BLANK INTENTIONALLY 6 13...

Page 172: ...BFISD 8079 Figure 6 4 4 Way Controller PCBA 6 14...

Page 173: ...4S08 Quad 2 Input Pos AND 4F 4N 4P 101625 IC 74S32 Quad 2 Input Pos OR 4L 101627 IC SN74S38 Quad 2 Input Pos NAND Buffer 1F 1G 101628 IC 74S64 4 2 3 2 Input AND OR Inv 1E 101629 IC SN74S74 Dual D Type...

Page 174: ...is R2 4B R3 1B Sockets 325005 003 Socket IC DIP 4 Leaf Cont Gold 14 Pos 2B 3B 3C 4C 5B 5C 325005 007 Socket IC DIP 4 Leaf Cont Gold 28 Pos 5J 6J 325005 010 Socket IC DIP 4 Leaf Cont Gold 40 Pos 5F 6F...

Page 175: ...BFISD 8079 THIS PAGE LEFT BLANK INTENTIONALLY 6 17...

Page 176: ...BFISD 8079 Figure 6 5 MTCS Controller PCBA 6 18...

Page 177: ...Input Pos OR 6K 101627 IC 74LS38 Quad 2 Input Pos NAND Buffer 1C 101628 IC 74S64 4 2 3 2 Input AND OR INV 2C 101629 IC SN74S74 Dual D Type F F 3B 5C 101630 IC 74S112 Dual J K Edge Trig F F 4C 6C 1H 10...

Page 178: ...Sequencer 2G 911010 001 IC PAL MTCS Controller 1J Resistors 111000 031 Resis Comp IK Ohm 5 Rl 2 6 7 8 13 111000 034 Resis Comp 82K Ohm 5 R4 111000 039 Resis Comp 22 Ohm 5 R5 111000 047 Resis Comp 200...

Page 179: ...BFISD 8079 THIS PAGE LEFT BLANK INTENTIONALLY 6 21...

Page 180: ...BFISD 8079 Figure 6 6 LAN Controller PCBA 6 22...

Page 181: ...D 3C 101625 IC 74S32 Quad 2 Input Pos OR 5G 6G 101627 IC SN74S38 Quad 2 Input Pos NAND Buffer 1E 1G 101628 IC 74S64 4 2 3 2 Input AND OR Inv 2G 101629 IC SN74S74 Dual D Type F F 1C 3G 101630 IC 74S112...

Page 182: ...cillator Xtal Clock 20 MHz Yl Resistors 111000 029 Resis Comp 330 Ohm 5 R7 8 111000 031 Resis Comp 1K Ohm 5 R3 4 5 6 9 13 111000 060 Resis Comp 4 7K Ohm 5 Rl 2 119000 003 Resis Ntwk DIP IK Ohm 16 Pin...

Page 183: ...BFISD 8079 THIS PAGE LEFT BLANK INTENTIONALLY 6 25...

Page 184: ...BFISD 8079 Figure 6 7 Winchester Drive Single Board Controller PCBA 6 26...

Page 185: ...EDATA SELECT MUX RES IF 10 6A 7A 0031 101635 4 000 EA A IC 74S175 QUAD D TYPE F F REL IE 4L 4M 8H 0032 101777 1 000 EA A IC 74S182 LOOK AHEAD CARRY GENERATOR RES 6H 0033 161OO9 11 000 EA A IC 74S240 O...

Page 186: ...BFISD 8079 Figure 6 8 Power Supply Input Module PCBA 6 28...

Page 187: ...ITCH ROCKER DPST SNAP IN PNL PT 10 AMP S1 0035 907485 001 1 000 EA X3 BRACKET PCB SWITCH MOUNTING 0036 315062 001 1 000 EA A KECPT AC PwH PALE CEE 6A 230V PC BKC MT Jl 0037 325042 001 1 000 EA A CONN...

Page 188: ...A A SWITCH ROCKER DPST SNAP IN PNL PT 10 AMP S1 0035 907485 001 1 000 EA X3 BRACKET PCB SWITCH MOUNTING 0036 315062 001 1 000 EA A RECPT AC PWR MALE CEE 6A 250V PC BRO MT Jl 0037 325042 001 1 000 EA A...

Page 189: ...BFISD 8079 THIS PAGE LEFT BLANK INTENTIONALLY 6 31...

Page 190: ...BFISD 8079 Figure 6 9 Power Supply Output Module PCBA 6 32...

Page 191: ...8 O022 1O1917 1 000 EA RES METAL FILM 125W 1 10 OK OHM REL R30 OO24 116OOO 2O5 1 000 5 P RES METAL FILM 125W 1 4 87K OHM INA R44 OO28 116000 107 1 000 EA P RES METAL FILM 125W 1 22 6K OHM REL R33 O 11...

Page 192: ...86 101304 1 000 EA 0 DIODE ZENER 1N5242B REL CR23 0087 131OO2 033 1 000 EA C DIODE ZENER 1N4747A REL CR18 0088 131001 007 1 000 EA 0 DIODE ZENER 500MW 1N5233B REL CR13 O090 101323 1 000 EA AX1 TRANS T...

Page 193: ...BFISD 8079 Figure 6 10 Power Supply Control Module PCBA 6 35...

Page 194: ...N FILM 25W 5 15K OHM RIO 37 0022 1110OO 065 8 000 EA J RES CARBON FILM 25W 5 2OK OHM R7 11 12 17 18 19 20 42 0023 111000 071 2 000 EA J RES CARBON FILM 25W 5 100K OHM R6 13 0024 111000 123 1 000 EA J...

Page 195: ...The Drive functions as an input output device in the Base Unit Access to data is pro vided by one moving head per disk surface Data is recorded on the disk sur faces using modified frequency modulatio...

Page 196: ...ent the disk from vibrating Also the Side 1 R W Head is pressed against the disk Moreover since the Interlock Arm presses the Latch Spring the Latch does not move and the disk cannot be ejected When t...

Page 197: ...BFISD 8079 Figure 7 3 Head Load Interlock Mechanism 7 3...

Page 198: ...plifier Circuit Write Circuit Digital System Stepper Motor Control Circuit Index Ready Circuit Write Protect Circuit Head Load Solenoid Control Circuit Brief explanations of the major circuits are pre...

Page 199: ...96 TPI The rotation of the Stepper Motor is converted to linear motion of the Read Write Heads by the Pulley Steel Belt assembly The DIRECTION IN signal cont rols the movement of the heads toward the...

Page 200: ...nother method named AH Automatic Head Load is that the Head Load Solenoid is drawn when the Drive is selected irrespective of the Head Load signal condition Figure 7 9 is a simplified schematic of the...

Page 201: ...otection notch is covered by an opaque cover Inserting a disk with the covered notch causes the photo transistor output to go to logic level low because the light from the LED does not reach the photo...

Page 202: ...BFISD 8079 7 8...

Page 203: ...he SELECT signal is ac tive Figure 7 15 is a simplified schematic of the Index Detection circuit 7 1 2 8 Ready Detector The Ready Detector is provided for monitoring the disk speed by the index pulse...

Page 204: ...sides of a track recorded by the read write coil The read write coils are rolled on the core chip and center tapped At the write operation time each bit of write data is alter nately distributed to e...

Page 205: ...lop to alternately turn on Hence the write current is supplied to the two halves of the read write coils alternately The alternating magnetic field corresponding to the data from the Central Mic ropro...

Page 206: ...ads and making the WRITE GATE signal a logic level high causes the Drive to enter the readable status The Read Circuit consists of an IC floppy amplifier and associated circuitry Figure 7 23 a simplif...

Page 207: ...plifier Figure 7 25 is a simplifed block diagram of the Read Write Select Circuit 7 1 2 13 Read Amplifier Circuit and Filter Network The read data signal is amplified by the preamplifier and the Flopp...

Page 208: ...fier is input to the Comparator The Comparator detects the zero crossover point of the signal thereby detecting the peak of the Active Differential Circuit input signal voltage Figure 7 27 is a simpli...

Page 209: ...s occurs in the outer cir cumference of the Drive The Timed Main Filter consists of a pulse generator a timed one shot MV and a timed main flip flop The pulse generator outputs a short pulse to trigge...

Page 210: ...ain flop flop Even if the timed one shot is clocked by an erroneous crossover the timed main flip flop output does not change because the erroneous crossover time is shorter than 2 2 microseconds The...

Page 211: ...4 0 volts 12 volts 8 3 volts 7 1 2 17 Power On Reset Circuit When the power is turned on to the Base Unit capacitor C figure7 31 begins charging to 3 volts When the capacitor voltage is lower than th...

Page 212: ...ding Time 25 ms Head Settling Time 20 ms Motor Start Time 800 ms Innermost Circumference Recording Density 5922 BPI Number of Tracks 160 both sides Track Density 96 TPI Track Radius Outer Circumferenc...

Page 213: ...overable read errors 1 in 1 000 000 000 bits Nonrecoverable read errors 1 in 1 000 000 000 000 bits Resistance Against Vibration in Operation Acceleration 1G Vibration Sweep 5 to 100 Hz Vibration Dire...

Page 214: ...y that the drive part number and serial number are correct 8 When practical store shipping containers for reuse 9 Record any damage and report damage to the applicable carrier 7 2 2 Equipment Placemen...

Page 215: ...hannel 2 test probe to the Drive test point labeled CHK2 connect the Trigger input to pin 49 of IC1 on the Main PCBA d Check that the start of the index burst is observed 200 microseconds from the beg...

Page 216: ...1 alternately and monitor the waveforms on both sides while moving the Stepper Motor to put the amplitude ratios small waveform divided by large waveform within the range prescribed by the label on th...

Page 217: ...n from track 06 to track 00 If necessary loosen the screw mounting the track 00 switch PCBA and adjust 7 2 4 4 Rotation Adjustment a After running the heads for 10 minutes load a normal diskette b Con...

Page 218: ...ves In the case of the daisy chain only the last Drive is terminated A resistance array close to connector J2 is provided for this termination The resistance array is remov able The alignment of the i...

Page 219: ...n the direction determined by the DIRECTION IN signal In usual cases this step speed is 3 ms track When the WRITE GATE signal is at logic level 0 the STEP signal is inhibited See the timing chart in f...

Page 220: ...BFISD 8079 Figure 7 33 Signal Interface Lines 7 26...

Page 221: ...erted into the Drive and is at logic level 0 during the normal select time Otherwise it is at logic level 1 TRACK 00 This signal goes to logic level 0 when the read write heads are positioned at track...

Page 222: ...the Drive For write protect the disk write prevention notch can be covered by an opaque label 7 3 2 Jumper Pin Selecting a jumper pin located on the Main PCBA permits a desired function to be used He...

Page 223: ...BFISD 8079 Figure 7 37 Factory Arrangement of Jumper 7 29...

Page 224: ...BFISD 8079 Note 1 In 48 T P I Model the period is 6 ms Note 2 In 48 T P I Model the period is 26 ms Figure 7 38 Drive Timing Diagram 7 30...

Page 225: ...BFISD 8079 7 31...

Page 226: ...BFISD 8079 7 32...

Page 227: ...BFISD 8079 7 33 34...

Page 228: ......

Page 229: ...to store and retrieve blocks of data records onto and from rotating disks thus pro viding storage for the MAI 2000 Series Computer System The Drive functions as an input output device in the Base Uni...

Page 230: ...BFISD 8079 Figure 8 1 Major Component Location 8 2...

Page 231: ...BFISD 8079 Figure 8 2 Head Disk Assembly 8 3...

Page 232: ...ing torque during handling Disk Electronics The disk electronics consists of three standard printed circuit board assemblies PCBAs the Master Electronics PCBA the Preamplifier PCBA and the Motor Contr...

Page 233: ...phase stepper motor is used to control the read write heads in the proper sequence at a rate and direction deter mined by a single chip microcomputer Index Logic The square wave output of the Hall sen...

Page 234: ...ode Single cylinder 18 milliseconds average 320 cylinders 1 035 milliseconds maximum Cylinder access 360 milliseconds average Slow pulse mode Single cylinder 23 milliseconds average 320 cylinders Step...

Page 235: ...tion no condensation Humidity Gradient 20 per hour 20 per hour 20 per hour Altitude 1 000 to 40 000 feet 0 to 40 000 feet 1 000 to 10 000 feet Vibration 0 2 inches peak peak 0 2 inches peak 0 006 inch...

Page 236: ...ore shipping containers for reuse 9 Record any damage and report damage to the applicable carrier 8 2 2 Equipment Placement Equipment placement consists of mounting the Drive in the Base Unit installi...

Page 237: ...connector J3 At power on the Drive motor takes 4 amperes at 12 volts dropping to 2 4 amperes maximum after 10 seconds For power up or power down sequences the 12 and 5 volt supplies may be applied or...

Page 238: ...se while Write Gate true Code 7 LED displays Static write fault condition Code 8 LED displays N A Code 9 LED displays Microcomputer self test failed Code 10 LED displays No index Code 11 LED displays...

Page 239: ...low through the bifiler winding from the center tap to either one end or the other When reading the ends of the coil are switched to the input of the read amplifier Data is erased by writing new data...

Page 240: ...BFISD 8079 8 12...

Page 241: ...gle chip microcomputer in the Master Electronics PCBA when the value of an internal 8 bit counter equals the desired stepper motor phase changes de termined by the Step and Direction In input signals...

Page 242: ...a Drive Select true signal is returned to the WDC via the data lines Step The Step signal pulse from the WDC is used in conjunction with the Direction In signal to move the stepper motor This pulse i...

Page 243: ...r The eight bit microprocessor is the intelligence of the WDC It monitors and controls the operation of the WDC State Machine The state machine controls and synchronizes the operation of the host inte...

Page 244: ...n it is low and when no dash appears at the end of a signal name the signal is active when it is high Some signal lines have two so called active or significant states When the level on the line is hi...

Page 245: ...ter that the controller is ready to conduct transactions on the SASI bus Table 8 6 Summary of SASI Bus Status Signals I 0 C D MSG DEFINITION High Low High The controller receives commands from the WDC...

Page 246: ...The controller must not be busy The WDC Bus Adapter must deactivate SEL before the end of the current command Table 8 9 Host Bus Data Signals NAME DRV RCVR DEFINITION DBO Tri State These are the eight...

Page 247: ...address is 0 The timing diagram in figure 8 7 shows the basic timing requirements Upon receiving both the SEL signal and DBO the WDC activates the BUSY signal As shown in the timing diagram both SEL a...

Page 248: ...y activating the ACK signal when a control byte is ready for the controller The control byte placed on the data bus by the WDC Bus Adapter must be stable within 250 nanoseconds after the ACK is activa...

Page 249: ...that the command is complete Figure 8 8 shows the data bus REQ and ACK timing See table 8 5 for I 0 C D and MSG definitions Figure 8 11 shows the format of these two bytes 8 3 3 3 Programming Informat...

Page 250: ...andon Bit 2 Buffer step option Computer Memories Inc and Rotating Mem ories Inc 200 microsecond pulse per step Bit 3 5 Spare Set to zero for future use Bit 6 If one during a read sector command the fa...

Page 251: ...ext to Last Status Byte BIT 7 6 5 4 3 2 1 0 0 0 0 d BUSY EQUAL CHECK 0 Bits 0 Set to zero 5 6 7 Bit 1 Check condition Sense is available Bit 2 Equal Set when any SEARCH is satisfied Bit 3 Busy Device...

Page 252: ...O d O O O O O Byte 2 0 0 0 0 0 0 0 0 Byte 3 0 0 0 0 0 0 0 0 Byte 4 0 0 0 0 0 0 0 0 Byte 5 0 0 0 0 0 0 0 0 Rezero Unit Class 0 Opcode 01 This command positions the read write R W arm to track 00 d driv...

Page 253: ...0 0 0 0 Byte 2 0 0 0 0 0 0 0 0 Byte 3 0 0 0 0 0 0 0 0 Byte 4 0 0 0 0 0 0 0 0 Byte 5 0 0 0 0 0 0 0 0 SENSE BYTES BIT 7 6 5 4 3 2 1 0 Byte 0 SEE BELOW Bits 0 3 Error Code Bits 4 6 Error Type Bit 7 Addr...

Page 254: ...drive Table 8 11 Type 1 Error Codes Controller HEX CODE DEFINITION 10 ID Read Error the controller detected a CRC error in the target ID field on the disk 11 Data Error the controller detected an unco...

Page 255: ...8 13 Request Sense Status Error Codes ERROR CODE HEX DEFINITION 00 No error detected command completed okay 01 No index detected from drive 02 No seek complete from drive 03 Write fault from drive 04...

Page 256: ...fields being written on the disk Any interleave number greater than 1 but less than the total number of sectors per track results in interleaved formatting A 00 in this field will cause the default i...

Page 257: ...ive times to establish a solid error syndrome Only then is correction attempted Correction is done directly into the data buffer transparent to the user d drive 0 or 1 BIT 7 6 5 4 3 2 1 0 Byte 0 0 0 0...

Page 258: ...a seek in progress will immediately complete with the busy command completion status bit 3 set This is done to allow the host to use the SASI bus to do other processing while waiting for seek to compl...

Page 259: ...ocks before and after the targeted block to determine the location of the target block The use of interleaved sectors and formatted skipped defects may complicate the determination of the error locati...

Page 260: ...0 0 Byte 5 0 0 0 0 0 0 0 0 Mode Select Class 0 Opcode 15 This command is used to specify FORMAT parameters and should always precede the FORMAT command A blown format error code 1C is detected when th...

Page 261: ...used to specify the data block size The block size must not be less than 256 or exceed the RAM buffer capacity which is IK bytes or 1 024 characters In this controller the block size must be set up wi...

Page 262: ...ead select The default value is two The Reduced Write Current Cylinder is the cylinder number beyond which the controller will assert the Reduced Write Current line The minimum value is 0 the maximum...

Page 263: ...hex must be specified If the drive parameter list is required the count should be 22 bytes 16 hex The returned information will be the four byte parameter list the Extent Descriptor List and the Driv...

Page 264: ...ffer in bytes READ DIAGNOSTIC is used to transfer data to the host and must immediately follow a SEND DIAGNOSTIC command which initiates the dump action Other wise the command will be rejected The dat...

Page 265: ...d The first byte of the data block specifies the particular function being requested The options available along with their associated codes are HEX CODE DEFINITION 60 Reinitialize Drive 61 Dump Hardw...

Page 266: ...tate is established by a controller reset These options once set stay in effect until the next reset They apply only to the Logical Unit Number addressed by the command The Set Read Error Handling Opt...

Page 267: ...hex this command will return the address of the block after the specified starting address at which a substantial delay in data transfer will be encountered e g a cylinder boundary Any value other th...

Page 268: ...cks and then verifies the data written on a block by block basis The verify function transfers no data to the host Since no data is transferred to the host during verify correctable data checks will b...

Page 269: ...omparison operation With invert on a SEARCH DATA EQUAL command would succeed on data not equal SEARCH DATA LOW would succeed on data greater or equal The invert bit allows SEARCH EQUAL inverted which...

Page 270: ...0 0 Byte 2 Logical Block Address MSB Byte 3 Logical Block Address Byte 4 Logical Block Address Byte 5 Logical Block Address LSB Byte 6 0 0 0 0 0 0 0 0 Byte 7 Number of Blocks Byte 8 Number of Blocks...

Page 271: ...Byte 9 Number of Records Byte 10 Number of Records Byte 11 Number of Records LSB Byte 12 Search Argument Length MSB Byte 13 Search Argument Length Byte 14 Search Field Displacement MSB Byte 15 Search...

Page 272: ...with a like size field in each record Pattern length must equal blocksize 20 to M 19 Data Pattern A variable length field of M bytes up to blocksize minus displacement bytes The pattern must be one b...

Page 273: ...result of the dc motor not starting the microcomputer attempts to reduce head disk static friction during a period of 8 seconds by moving the positioner four times one track in alternate directions T...

Page 274: ...3 More than one read write head selected or 4 12 volt supply below 10 3 volts or 5 5 volt supply below 4 5 volts The operational error codes are detailed in the following paragraphs Codes 4 and 6 Whi...

Page 275: ...circuit between Motor Reinstall PCBA Speed Control PCBA and casting Fault in stepper motor control Replace the Master Electronics circuitry PCBA or the Motor Speed Control PCBA 3 4 Brake failure Repla...

Page 276: ...ure before attempting removal or replacement There is no preventive maintenance on the Drive and there are no adjustments Field repair is restricted to replacement of the Master Electronics PCBA the M...

Page 277: ...BFISD 8079 Figure 8 12 Winchester Drive Assembly 8 49...

Page 278: ...BFISD 8079 Figure 8 13 Head Disk Disassembly 8 50...

Page 279: ...brake connector J6 from the Motor Speed Control PCBA 3 Using the box spanner remove the two nuts securing the brake to the casting and remove the brake 4 To replace the brake position the replacement...

Page 280: ...ment Motor Speed Control PCBA insert the ground tab and tighten the rear stand off Insert and tighten the left standoff 6 Reconnect stepper motor connector J8 dc motor connector J9 and brake connector...

Page 281: ...BFISD 8079 Motor Speed Control PCBA Schematic 3 53...

Page 282: ...BFISD 8079 Master Electronics PCBA Schematic 1 of 4 3 54...

Page 283: ...BFISD 8079 Master Electronics PCBA Schematic 2 of 4 8 55...

Page 284: ...BFISD 8079 Master Electronics PCBA Schematic 3 of 4 8 56...

Page 285: ...BFISD 8079 Master Electronics PCBA Schematic 4 of 4 8 57...

Page 286: ...BFISD 8079 Motor Speed Control PCBA Layout 8 58...

Page 287: ...BFISD 8079 Master Electronics PCBA Layout 8 59 60...

Page 288: ......

Page 289: ...viding storage for the MAI 2000 Series Computer System The drive functions as an input out put device in the Base Unit The 50 MB Winchester Drive contains four magnetic disks and has a total data stor...

Page 290: ...estraining torque during handling Disk Electronics The disk electronics consists of three standard printed circuit board assemblies PCBAs the Device Electronics PCBA the Preamplifier PCBA and the Moto...

Page 291: ...ads in the proper sequence at a rate and direction determined by a single chip microcomputer Position reference is made to tracks recorded on a dedicated servo surface on the disk nearest the drive mo...

Page 292: ...per second Seek Time Track to track 6 milliseconds Average 30 milliseconds One third stroke 33 milliseconds Maximum 60 milliseconds Rotation Latency Average 8 33 milliseconds Maximum 16 67 millisecon...

Page 293: ...inches peak 0 006 inches peak displacement peak displacement peak displacement 5 Hz to 10 Hz 5 Hz to 31 Hz 5 Hz to 60 Hz 1 G peak 1 G peak 0 5 G peak 10 Hz to 44 Hz 31 Hz to 69 Hz 40 Hz to 300 Hz 0 01...

Page 294: ...cord any damage and report damage to the applicable carrier 9 2 2 Equipment Placement Equipment placement consists of mounting the drive in the Base Unit installing the Winchester Drive Controller mou...

Page 295: ...volts to the drive Ground connector J4 connects the drive inner chassis ground to the system ground J4 is located on the Head Disk Assembly near the left hand shock mount as viewed from the rear of th...

Page 296: ...5 Write Gate WDC 8 7 Seek Complete Drive 10 9 Track 00 Drive 12 11 Write Fault Drive 14 13 Head Select 0 WDC 16 15 Reserved 18 17 Head Select 1 WDC 20 19 Index Drive 22 21 Ready Drive 24 23 Step WDC...

Page 297: ...e 3 4 Reserved 5 6 Reserved 7 8 Reserved 9 10 Reserved 11 Ground 12 Ground 13 MFM Write Data WDC 14 MFM Write Data WDC 15 Ground 16 Ground 17 MFM Read Data Drive 18 MFM Read Data Drive 19 Ground 20 Gr...

Page 298: ...the Base Unit cover and push in to disengage the the plastic latch Repeat with the left hand side and remove the cover 3 Remove the Memory Array PCBAs located in the front right hand corner of the CMB...

Page 299: ...n cable coming the WDC Bus Adapter into connector J4 on the WDC PCBA 11 Plug the 4 pin power connector coming from the WDC Bus Adapter into J3 on the WDC PCBA 12 Plug the WDC Bus Adapter PCBA into the...

Page 300: ...BFISD 8079 Figure 9 4 Location of Jumpers on the Winchester Drive Controller PCBA 9 12...

Page 301: ...plies may be applied or removed in any order However the rise time of the 5 volts must be less than 50 milliseconds for proper op eration of the power on reset circuits On power up the drive performs...

Page 302: ...p connection causing current to flow through the bifiler winding from the center tap to either one end or the other When reading the ends of the coil are switched to the input of the read amplifier Da...

Page 303: ...BFISD 8079 9 15...

Page 304: ...current d The 5 volt supply is below 4 5 volts e Motor speed exceeds 1 tolerance after the power up sequence is completed f Write Gate is true while Seek Complete is false or the heads are not positi...

Page 305: ...is ready to read or write with or without an implied seek and the other lines are valid Ready remains true until power off or until there is a Write Fault Drive Select The Drive Select signal from th...

Page 306: ...interface The two boards are piggybacked with the WDC PCBA mounted above the component side of the WDC Bus Adapter PCBA They are electrically interconnected by a 50 pin flat ribbon connector at J4 and...

Page 307: ...ignal is that state which is required for a given operation hen a dash is appended to the end of a signal name the signal is active when t is low When no dash appears at the end of a signal name the s...

Page 308: ...e controller is ready to conduct transactions on the SASI bus Table 9 8 Summary of SASI Bus Status Signals I 0 C D MSG DEFINITION High Low High The controller receives commands from the WDC Bus Adapte...

Page 309: ...The controller must not be busy The WDC Bus Adapter must deactivate SEL before the end of the current command Table 9 11 Host Bus Data Signals NAME DRV RCVR DEFINITION DBO Tri State These are the eigh...

Page 310: ...ress is 0 The timing diagram in figure 9 10 shows the basic timing requirements Upon receiving both the SEL signal and DBO the WDC activates the BUSY signal As shown in the timing diagram both SEL and...

Page 311: ...activating the ACK signal when a control byte is ready for the controller The control byte placed on the data bus by the WDC Bus Adapter must be stable within 250 nanoseconds after the ACK is activate...

Page 312: ...that the command is complete Figure 9 11 shows the data bus REQ and ACK timing See table 9 8 for I 0 C D and MSG definitions Figure 9 13 shows the format of these two bytes 9 3 3 3 Programming Informa...

Page 313: ...andon Bit 2 Buffer step option Computer Memories Inc and Rotating Mem ories Inc 200 microsecond pulse per step Bit 3 5 Spare Set to zero for future use Bit 6 If one during a read sector command the fa...

Page 314: ...ogical Address High Middle Low The logical address of the drive is computed by using the following equation Logical Address CYADR HDCYL HDADR BKTRK BKADR Where CYADR Cylinder Address HDADR Head Addres...

Page 315: ...Byte 3 0 0 0 0 0 0 00 Byte 4 0 0 0 0 0 0 00 Byte 5 0 0 0 0 0 0 00 Rezero Unit Class 0 Opcode 01 This command positions the read write R W arm to track 00 d drive 0 or 1 BIT 7 6 5 4 3 2 1 0 Byte 0 0 0...

Page 316: ...Byte 2 0 0 0 0 0 0 0 0 Byte 3 0 0 0 0 0 0 0 0 Byte 4 0 0 0 0 0 0 0 0 Byte 5 0 0 0 0 0 0 0 0 SENSE BYTES BIT 7 6 5 4 3 2 1 0 Byte 0 SEE BELOW Bits 0 3 Error Code Bits 4 6 Error Type Bit 7 Address valid...

Page 317: ...drive Table 9 13 Type 1 Error Codes Controller HEX CODE DEFINITION 10 ID Read Error the controller detected a CRC error in the target ID field on the disk 11 Data Error the controller detected an unco...

Page 318: ...No seek complete from drive 03 Write fault from drive 04 Drive not ready after it was selected 06 Track 00 not found 10 ID field read error 11 Uncorrectable data error 12 ID address mark not found 13...

Page 319: ...fields being written on the disk Any interleave number greater than 1 but less than the total number of sectors per track results in interleaved formatting A 00 in this field will cause the default i...

Page 320: ...ive times to establish a solid error syndrome Only then is correction attempted Correction is done directly into the data buffer transparent to the user d drive 0 or 1 BIT 7 6 5 4 3 2 1 0 Byte 0 0 0 0...

Page 321: ...a seek in progress will immediately complete with the busy command completion status bit 3 set This is done to allow the host to use the SASI bus to do other processing while waiting for seek to compl...

Page 322: ...ks before and after the targeted block to determine the location of the target block The use of inter leaved sectors and formatted skipped defects may complicate the deter mination of the error locati...

Page 323: ...4 0 0 0 0 0 0 0 0 Byte 5 0 0 0 0 0 0 0 0 Mode Select Class 0 Opcode 15 This command is used to specify FORMAT parameters and should always precede the FORMAT command A blown format error code 1C is d...

Page 324: ...s optional but if present it must be complete and the items must be within the limits stated If these parameters are not supplied the format operation will use previously supplied values if available...

Page 325: ...Byte 5 Reduced Write Current Cylinder LSB Byte 6 Write Precompensation Cylinder MSB Byte 7 Write Precompensation Cylinder LSB Byte 8 Landing Zone Position Byte 9 Step Pulse Output Rate Code The Landi...

Page 326: ...e number of data bytes to be returned from the command A minimum of 12 bytes OC hex must be specified If the drive parameter list is required the count should be 22 bytes 16 hex The returned informati...

Page 327: ...ffer in bytes READ DIAGNOSTIC is used to transfer data to the host and must immediately follow a SEND DIAGNOSTIC command which initiates the dump action Other wise the command will be rejected The dat...

Page 328: ...d The first byte of the data block specifies the particular function being requested The options available along with their associated codes are HEX CODE DEFINITION 60 Reinitialize Drive 61 Dump Hardw...

Page 329: ...is established by a controller reset These options once set stay in effect until the next reset They apply only to the Logical Unit Number addressed by the command The Set Read Error Handling Options...

Page 330: ...hex this command will return the address of the block after the specified starting address at which a substantial delay in data transfer will be encountered e g a cylinder boundary Any value other th...

Page 331: ...cks and then verifies the data written on a block by block basis The verify function transfers no data to the host Since no data is transferred to the host during verify correctable data checks will b...

Page 332: ...omparison operation With invert on a SEARCH DATA EQUAL command would succeed on data not equal SEARCH DATA LOW would succeed on data greater or equal The invert bit allows SEARCH EQUAL inverted which...

Page 333: ...SB Byte 3 Logical Block Address Byte 4 Logical Block Address Byte 5 Logical Block Address LSB Byte 6 0 0 0 0 0 0 0 0 Byte 7 Number of Blocks Byte 8 Number of Blocks Byte 9 0 0 0 0 0 0 0 0 The argument...

Page 334: ...First Record Offset LSB Byte 8 Number of Records MSB Byte 9 Number of Records Byte 10 Number of Records Byte 11 Number of Records LSB Byte 12 Search Argument Length MSB Byte 13 Search Argument Length...

Page 335: ...en the smaller value is encountered 12 to 13 Search Argument Length bytes The number of bytes in the following search argument Must equal the pattern length plus six 14 to 17 Search Field Displacement...

Page 336: ......

Page 337: ...BFISD 8079 SECTION X REFERENCE DATA FIGURE TITLE PAGE 10 1 PCBA Central Microprocessor Board 10 2 10 2 Logic Diagram Central Microprocessor Board 59 drawings 10 3 10 1...

Page 338: ...BFISD 8079 PCBA Central Microprocessor Board Figure 10 1 PCBA Central Microprocessor Board 10 2...

Page 339: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 1 of 58 10 3...

Page 340: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 2 of 58 10 4...

Page 341: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 3 of 58 10 5...

Page 342: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 4 of 58 10 6...

Page 343: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 5 of 58 10 7...

Page 344: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 6 of 58 10 8...

Page 345: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 7 of 58 10 9...

Page 346: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 8 of 58 10 10...

Page 347: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 9 of 58 10 11...

Page 348: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 10 of 58 10 12...

Page 349: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 11 of 58 10 13...

Page 350: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 12 of 58 10 14...

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Page 356: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 18 of 58 10 20...

Page 357: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 19 of 58 10 21...

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Page 359: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 21 of 58 10 23...

Page 360: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 22 of 58 10 24...

Page 361: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 23 of 58 10 25...

Page 362: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 24 of 58 10 26...

Page 363: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 25 of 58 10 27...

Page 364: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 26 of 58 10 28...

Page 365: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 27 of 58 10 29...

Page 366: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 28 of 5 10 30...

Page 367: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 28 1 of 58 10 31...

Page 368: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 29 of 58 10 32...

Page 369: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 30 of 58 10 33...

Page 370: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 31 of 58 10 34...

Page 371: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 32 of 58 10 35...

Page 372: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 33 of 58 10 36...

Page 373: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 34 of 58 10 37...

Page 374: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 35 of 58 10 38...

Page 375: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 36 of 58 10 39...

Page 376: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 37 of 58 10 40...

Page 377: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 38 of 58 10 41...

Page 378: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 39 of 58 10 42...

Page 379: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 40 of 58 10 43...

Page 380: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 41 of 58 10 44...

Page 381: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 42 of 58 10 45...

Page 382: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 43 of 58 10 46...

Page 383: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 44 of 58 10 47...

Page 384: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 45 of 58 10 48...

Page 385: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 46 of 58 10 49...

Page 386: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 47 of 58 10 50...

Page 387: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 48 of 58 10 51...

Page 388: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 49 of 58 10 52...

Page 389: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 50 of 58 10 53...

Page 390: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 51 of 58 10 54...

Page 391: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 52 of 58 10 55...

Page 392: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 53 of 58 10 56...

Page 393: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 54 of 58 10 57...

Page 394: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 55 of 58 10 58...

Page 395: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 56 of 58 10 59...

Page 396: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 57 of 58 10 60...

Page 397: ...BFISD 8079 Figure 10 2 Logic Diagram Central Microprocessor Board Sheet 58 of 58 10 61 62...

Page 398: ......

Page 399: ...BFISD 8079 Memory Array PCBA Figure 10 3 Logic Diagram Memory Array PCBA 903369 Rev A Sht 1 of 9 10 63...

Page 400: ...BFISD 8079 Figure 10 3 Logic Diagram Memory Array PCBA 903369 Rev A Sht 2 of 9 10 64...

Page 401: ...BFISD 8079 Figure 10 3 Logic Diagram Memory Array PCBA 903369 Rev A Sht 3 of 9 10 65...

Page 402: ...BFISD 8079 Figure 10 3 Logic Diagram Memory Array PCBA 903369 Rev A Sht 4 of 9 10 66...

Page 403: ...BFISD 8079 Figure 10 3 Logic Diagram Memory Array PCBA 903369 Rev A Sht 5 of 9 10 67...

Page 404: ...BFISD 8079 Figure 10 3 Logic Diagram Memory Array PCBA 903369 Rev A Sht 6 of 9 10 68...

Page 405: ...BFISD 8079 Figure 10 3 Logic Diagram Memory Array PCBA 903369 Rev A Sht 7 of 9 10 69...

Page 406: ...BFISD 8079 Figure 10 3 Logic Diagram Memory Array PCBA 903369 Rev A Sht 8 of 9 10 70...

Page 407: ...BFISD 8079 Figure 10 3 Logic Diagram Memory Array PCBA 903369 Rev A Sht 9 of 9 10 71 72...

Page 408: ......

Page 409: ...BFISD 8079 Winchester Disk Controller Figure 10 4 Logic Diagram Winchester Disk Controller PCBA 903461 Rev C Sht 1 of 15 10 73...

Page 410: ...BFISD 8079 Figure 10 4 Logic Diagram Winchester Disk Controller PCBA 903461 Rev C Sht 2 of 15 10 74...

Page 411: ...BFISD 8079 Figure 10 4 Logic Diagram Winchester Disk Controller PCBA 903461 Rev C Sht 3 of 15 10 75...

Page 412: ...BFISD 8079 Figure 10 4 Logic Diagram Winchester Disk Controller PCBA 903461 Rev C Sht 4 of 15 10 76...

Page 413: ...BFISD 8079 Figure 10 4 Logic Diagram Winchester Disk Controller PCBA 903461 Rev C Sht 5 of 15 10 77...

Page 414: ...BFISD 8079 Figure 10 4 Logic Diagram Winchester Disk Controller PCBA 903461 Rev C Sht 6 of 15 10 78...

Page 415: ...BFISD 8079 Figure 10 4 Logic Diagram Winchester Disk Controller PCBA 903461 Rev C Sht 7 of 15 10 79...

Page 416: ...BFISD 8079 Figure 10 4 Logic Diagram Winchester Disk Controller PCBA 903461 Rev C Sht 8 of 15 10 80...

Page 417: ...BFISD 8079 Figure 10 4 Logic Diagram Winchester Disk Controller PCBA 903461 Rev C Sht 9 of 15 10 81...

Page 418: ...BFISD 8079 Figure 10 4 Logic Diagram Winchester Disk Controller PCBA 903461 Rev C Sht 10 of 15 10 82...

Page 419: ...BFISD 8079 Figure 10 4 Logic Diagram Winchester Disk Controller PCBA 903461 Rev C Sht 11 of 15 10 83...

Page 420: ...BFISD 8079 Figure 10 4 Logic Diagram Winchester Disk Controller PCBA 903461 Rev C Sht 12 of 15 10 84...

Page 421: ...PAGE MISSING This Page was misprinted in my original documentation is was page 10 85 and 10 87 printed on one page 10 85...

Page 422: ...PAGE MISSING This Page was misprinted in my original documentation is was page 10 85 and 10 63 printed on one page 10 86...

Page 423: ...BFISD 8079 Figure 10 4 Logic Diagram Winchester Disk Controller PCBA 903461 Rev C Sht 15 of 15 10 87 88...

Page 424: ......

Page 425: ...BFISD 8079 4 Way Controller Figure 10 5 Logic Diagram 4 Way Controller PCBA 903391 Rev E Sht 1 of 10 10 89...

Page 426: ...BFISD 8079 Figure 10 5 Logic Diagram 4 Way Controller PCBA 903391 Rev E Sht 2 of 10 10 90...

Page 427: ...BFISD 8079 Figure 10 5 Logic Diagram 4 Way Controller PCBA 903391 Rev E Sht 3 of 10 10 91...

Page 428: ...BFISD 8079 Figure 10 5 Logic Diagram 4 Way Controller PCBA 903391 Rev E Sht 4 of 10 10 92...

Page 429: ...BFISD 8079 Figure 10 5 Logic Diagram 4 Way Controller PCBA 903391 Rev E Sht 5 of 10 10 93...

Page 430: ...BFISD 8079 Figure 10 5 Logic Diagram 4 Way Controller PCBA 903391 Rev E Sht 6 of 10 10 94...

Page 431: ...BFISD 8079 Figure 10 5 Logic Diagram 4 Way Controller PCBA 903391 Rev E Sht 7 of 10 10 95...

Page 432: ...BFISD 8079 Figure 10 5 Logic Diagram 4 Way Controller PCBA 903391 Rev E Sht 8 of 10 10 96...

Page 433: ...BFISD 8079 Figure 10 5 Logic Diagram 4 Way Controller PCBA 903391 Rev E Sht 9 of 10 10 97...

Page 434: ...BFISD 8079 Figure 10 5 Logic Diagram 4 Way Controller PCBA 903391 Rev E Sht 10 of 10 10 98...

Page 435: ...BFISD 8079 Local Area Network Controller Figure 10 6 Logic Diagram Local Area Network Controller PCBA 903410 Rev C Sht 2 of 20 10 99...

Page 436: ...BFISD 8079 Figure 10 6 Logic Diagram Local Area Network Controller PCBA 903410 Rev C Sht 3 of 20 10 100...

Page 437: ...BFISD 8079 Figure 10 6 Logic Diagram Local Area Network Controller PCBA 903410 Rev C Sht 4 of 20 10 101...

Page 438: ...BFISD 8079 Figure 10 6 Logic Diagram Local Area Network Controller PCBA 903410 Rev C Sht 5 of 20 10 102...

Page 439: ...BFISD 8079 Figure 10 6 Logic Diagram Local Area Network Controller PCBA 903410 Rev C Sht 6 of 20 10 103...

Page 440: ...BFISD 8079 Figure 10 6 Logic Diagram Local Area Network Controller PCBA 903410 Rev C Sht 7 of 20 10 104...

Page 441: ...BFISD 8079 Figure 10 6 Logic Diagram Local Area Network Controller PCBA 903410 Rev C Sht 8 of 20 10 105...

Page 442: ...BFISD 8079 Figure 10 6 Logic Diagram Local Area Network Controller PCBA 903410 Rev C Sht 9 of 20 10 106...

Page 443: ...BFISD 8079 Figure 10 6 Logic Diagram Local Area Network Controller PCBA 903410 Rev C Sht 10 of 20 10 107...

Page 444: ...BFISD 8079 Figure 10 6 Logic Diagram Local Area Network Controller PCBA 903410 Rev C Sht 11 of 20 10 108...

Page 445: ...BFISD 8079 Figure 10 6 Logic Diagram Local Area Network Controller PCBA 903410 Rev C Sht 12 of 20 10 109...

Page 446: ...BFISD 8079 Figure 10 6 Logic Diagram Local Area Network Controller PCBA 903410 Rev C Sht 13 of 20 10 110...

Page 447: ...BFISD 8079 Figure 10 6 Logic Diagram Local Area Network Controller PCBA 903410 Rev C Sht 14 of 20 10 111...

Page 448: ...BFISD 8079 Figure 10 6 Logic Diagram Local Area Network Controller PCBA 903410 Rev C Sht 15 of 20 10 112...

Page 449: ...BFISD 8079 Figure 10 6 Logic Diagram Local Area Network Controller PCBA 903410 Rev C Sht 16 of 20 10 113...

Page 450: ...BFISD 8079 Figure 10 6 Logic Diagram Local Area Network Controller PCBA 903410 Rev C Sht 17 of 20 10 114...

Page 451: ...BFISD 8079 Figure 10 6 Logic Diagram Local Area Network Controller PCBA 903410 Rev C Sht 18 of 20 10 115...

Page 452: ...BFISD 8079 Figure 10 6 Logic Diagram Local Area Network Controller PCBA 903410 Rev C Sht 19 of 20 10 116...

Page 453: ...BFISD 8079 Figure 10 6 Logic Diagram Local Area Network Controller PCBA 903410 Rev C Sht 20 of 20 10 117 118...

Page 454: ......

Page 455: ...BFISD 8079 Magnetic Cartridge Streamer Controller Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 2 of 24 10 119...

Page 456: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 3 of 24 10 120...

Page 457: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 4 of 24 10 121...

Page 458: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 5 of 24 10 122...

Page 459: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 6 of 24 10 123...

Page 460: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 7 of 24 10 124...

Page 461: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 8 of 24 10 125...

Page 462: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 9 of 24 10 126...

Page 463: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 10 of 24 10 127...

Page 464: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 11 of 24 10 128...

Page 465: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 12 of 24 10 129...

Page 466: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 13 of 24 10 130...

Page 467: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 14 of 24 10 131...

Page 468: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 15 of 24 10 132...

Page 469: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 16 of 24 10 133...

Page 470: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 17 of 24 10 134...

Page 471: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 18 of 24 10 135...

Page 472: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 19 of 24 10 136...

Page 473: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 20 of 24 10 137...

Page 474: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 21 of 24 10 138...

Page 475: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 22 of 24 10 139...

Page 476: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 23 of 24 10 140...

Page 477: ...BFISD 8079 Figure 10 7 Logic Diagram Magnetic Cartridge Streamer Controller PCBA 903427 Rev A 24 of 24 10 141 142...

Page 478: ......

Page 479: ...BFISD 8079 Power Supply Input Module Figure 10 8 Logic Diagram Power Supply Input Module PCBA 903443 Rev E Sht 1 of 1 10 143 144...

Page 480: ......

Page 481: ...BFISD 8079 Power Supply Output Module Figure 10 9 Logic Diagram Power Supply Output Module PCBA 903446 Rev B Sht 2 of 6 10 145...

Page 482: ...BFISD 8079 Figure 10 9 Logic Diagram Power Supply Output Module PCBA 903446 Rev B Sht 3 of 6 10 146...

Page 483: ...BFISD 8079 Figure 10 9 Logic Diagram Power Supply Output Module PCBA 903446 Rev B Sht 4 of 6 10 147...

Page 484: ...BFISD 8079 Figure 10 9 Logic Diagram Power Supply Output Module PCBA 903446 Rev B Sht 5 of 6 10 148...

Page 485: ...BFISD 8079 Figure 10 9 Logic Diagram Power Supply Output Module PCBA 903446 Rev B Sht 6 of 6 10 149 150...

Page 486: ......

Page 487: ...BFISD 8079 Power Supply Control Module Figure 10 10 Logic Diagram Power Supply Control Module PCBA 903404 Rev A Sht 2 of 3 10 151...

Page 488: ...BFISD 8079 Figure 10 10 Logic Diagram Power Supply Control Module PCBA 903404 Rev A Sht 3 of 3 10 152...

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MAI Basic Four 2000 Series, Service Manual

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