MAI Basic Four 2000 Series, Service Manual, Page: 63 / 488

BFISD 8079
3.2.5.3 Parity Error Interrupt Cycle
When a parity error occurs, the SINT7- output from the parity logic PAL (6Y) is
asserted. SINT7- latches a flip-flop whose Q output then sends a low to the 7
input of an 8-to-3 priority encoder. (Refer to the CMB Logic Diagram, sheet
22.) The output forms an interrupt request via three 68010 interrupt request
lines, IPLO- through IPL2-. Since no other interrupt can have a greater 68010
priority, an interrupt acknowledge cycle will begin upon completion of the cur-
rent processor instruction.
The 68010 places the interrupt priority level on the lines carrying the three
least significant address bits. These are decoded by a 1-of-8 data selector.
For interrupt level 7, the CVPA- output is low. In response to CVPA- low, the
68010 generates a vector number based on the interrupt level number. The con-
tent of the vector number is fetched from RAM and then loaded into the 68010
program counter, and normal instruction execution commences in an interrupt
service routine. (Interrupt logic is discussed further in paragraph 3.2.6.)
System software now can read the status register and discover that it was a
memory parity error that initiated the interrupt cycle. The program can then go
on to read the parity error register and find the base address of the RAM that
caused the memory fault.
3.2.6 Interrupt Logic
There are at least two general strategies for control of input/output (I/O) in
a computer system. One is initiated by the processor (program-controlled), and
the other is initiated by the I/O port (interrupt-driven). The difference be-
tween the two is in the method used to determine when a port has completed an
operation. In the case of interrupt-driven I/O, the port provides an interrupt
request signal to the processor (CPU) when an operation has been completed.
Then, when the processor is at a point where the program in process can be sus-
pended temporarily, the processor will commence with I/O operations. Upon com-
pletion of I/O operations, the processor continues with the suspended program.
Since there are several circuits and I/O devices in the Model 4108 Base Unit
that require interrupt processing, a technique for identifying the source and
the priority level of the interrupt request is provided. The method used is
vectored interrupts.
Generally, this means that a device requesting an interrupt is required to send
a vector number to the processor for translation into the starting address of
the appropriate interrupt service routine. Specifically, the requesting device
sends a priority number to the 68010 as part of the interrupt request signal;
then it sends the vector number as a separate signal after receiving an inter-
rupt acknowledge signal from the 68010.
There are seven levels of interrupts available on the 68010, with level 7 being
the highest priority. In the Base Unit, levels 2 and 4 may be auto-vectored or
bus-vectored (both are explained in paragraph 3.2.6.1); levels 1, 3, 5, 6 and 7
are always autovectored. The seven interrupt levels are configured as follows:
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