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AD3V

P. 2 / 8           EM-1389 Rev.13

         5-2-55, Minamitsumori, Nishinari-ku, Osaka 557-0063 JAPAN

Phone: +81(6)6659-8201   Fax: +81(6)6659-8510   E-mail: [email protected]

3

4

5

6

2

1

8

7

80 (3.15)

50 (1.97)

103 (4.06)

123 (4.84)

[3.3 (.13)]

80 (3.15)

20

(.79)

35.4 (1.39)

40 (1.57)

50 (1.97)

7.8 (.31)

CLAMP
(top & bottom)

DIN RAIL
35mm wide

2–4.5 (.18) dia.

MTG HOLE

15 (.59) deep

8–M3.5

SCREW

•When mounting, no extra space is needed between units.

16

(.63)

55 (2.17) min.

5

6

2

1

8

7

3

4

12 (.47)

INPUT RESISTOR

(model: REM)

Input shunt resistor attached 
for current input.

■ 

TERMINAL ASSIGNMENT  mm (inch)

■ 

CONNECTION DIAGRAM

U(+)

V(–)

POWER

7

8

CONNECTOR

+

*

INPUT

R

4

3

*

Input shunt resistor attached for current input.

OUTPUT

OUTPUT CONNECTOR (26-pin)

■ 

BCD OUTPUT

■ 

BINARY, TWO'S COMPLEMENT OUTPUTS

TERMINAL CONNECTIONS

Connect the unit as in the diagram below or refer to the connection diagram label on top of the unit.
When an input resistor is provided with the module, attach it together with input wiring to the input screw terminals.

■ 

DIMENSIONS  mm (inch)

PIN NO.

ASSIGNMENT

PIN NO.

ASSIGNMENT

1

B

0

17

COM (–)

2

B

1

18

COM (–)

3

B

2

19

OVF

4

B

3

20

POL

5

B

4

21

DAV

6

B

5

22

HOLD*

1

7

B

6

23

P

*

2

8

B

7

24

P

1

9

B

8

25

P

2

10

B

9

26

P

3

11

B

10

12

B

11

13

B

12

14

B

13

15

B

14

16

B

15

*1. HOLD signal is for input, the others are for output.
*2. P

 0

 corresponds to B

0

 through B

3

, P

1

 to B

4

 through B

7

, P

to

B

8

 through B

11

, P

to B

12

 through B

15

.

Note: With the number of bits set to 14 (or 12, 10, 8) with
ITEM 10, Pin No. 1 – 14 (or 1 – 12, 1 – 10, 1 – 8) are valid.

PIN NO.

ASSIGNMENT

PIN NO.

ASSIGNMENT

1

×

 10

0

17

COM (–)

2

×

 10

0

18

COM (–)

3

×

 10

0

19

OVF

4

×

 10

0

20

POL

5

×

 10

1

21

DAV

6

×

 10

1

22

HOLD*

1

7

×

 10

1

23

P

*

2

8

×

 10

1

24

P

1

9

×

 10

2

25

P

2

10

×

 10

2

26

P

3

11

×

 10

2

12

×

 10

2

13

×

 10

3

14

×

 10

3

15

×

 10

3

16

×

 10

3

*1. HOLD signal is for input, the others are for output.
*2. P

0

 corresponds to n 

×

 10

0

, P

1

 to n 

×

 10

1

, P

to n 

×

 10

2

, P

to n

×

 10

3

.

Note: With the number of bits set to 14 (or 12, 10, 8) with
ITEM 10, Pin No. 1 – 14 (or 1 – 12, 1 – 10, 1 – 8) are valid.

Summary of Contents for AD3V

Page 1: ...ck the power rating for the unit on the specification label Rating 100 240V AC 85 264V 47 66 Hz approx 5VA Rating 12 24V DC 10 8 26 4V approx 4W Rating 110V DC 85 150V approx 4W UNPLUGGING THE UNIT Before you remove the unit from its base socket or mount it turn off the power supply and signal input for safety INSTRUCTION MANUAL MODEL AD3V Input Resistor A D CONVERTER 16 bit resolution Connection ...

Page 2: ...nput resistor is provided with the module attach it together with input wiring to the input screw terminals DIMENSIONS mm inch PIN NO ASSIGNMENT PIN NO ASSIGNMENT 1 B0 17 COM 2 B1 18 COM 3 B2 19 OVF 4 B3 20 POL 5 B4 21 DAV 6 B5 22 HOLD 1 7 B6 23 P0 2 8 B7 24 P1 9 B8 25 P2 10 B9 26 P3 11 B10 12 B11 13 B12 14 B13 15 B14 16 B15 1 HOLD signal is for input the others are for output 2 P 0 corresponds to...

Page 3: ...0 ms approx 1 ms HOLD INPUT Data output is halt during HOLD input DAV is output during DATA output Varies by individual module Set to n times with ITEM 20 Selectable with ITEM 17 CONNECTION EXAMPLES AD3V 26 pin CONNECTOR H 4 5V or more L 0 5V or less OUTPUT COMMON AD3V 26 pin CONNECTOR Max collector emitter voltage 30V DC Max collector current 30mA V OUTPUT COMMON LOAD CMOS LEVEL 5V CMOS OPEN COLL...

Page 4: ...DIGITAL OUTPUT FS ANALOG INPUT INPUT OUTPUT RELATIONSHIP EXAMPLES FS FS stands for 15 of the input range which is configured by ITEM22 0 input voltage and ITEM23 100 input voltage FS stands for 115 of the input range OVF When one of the following conditions is true the digital output overflows OVF 1 When the input signal is out of the range between FS and FS 2 When the display value output signal ...

Page 5: ...i Lo Hi 8 Hi Lo Lo Lo Lo Hi 9 Hi Lo Lo Hi Hi Lo 10 Hi Lo Hi Lo Hi Lo 11 Hi Lo Hi Hi Lo Hi 12 Hi Hi Lo Lo Hi Lo 13 Hi Hi Lo Hi Lo Hi 14 Hi Hi Hi Lo Lo Hi 15 Hi Hi Hi Hi Hi Lo Negative Logic I14 1 Lo True Hi False DATA 8 4 2 1 PARITY Even I12 0 Odd I12 1 0 Hi Hi Hi Hi Hi Lo 1 Hi Hi Hi Lo Lo Hi 2 Hi Hi Lo Hi Lo Hi 3 Hi Hi Lo Lo Hi Lo 4 Hi Lo Hi Hi Lo Hi 5 Hi Lo Hi Lo Hi Lo 6 Hi Lo Lo Hi Hi Lo 7 Hi Lo...

Page 6: ...of bits 0 0 16 bits 1 14 bits 2 12 bits 3 10 bits 4 8 bits 11 2 0 1 2 Parity check 0 0 Disable 1 Enable Parity per each digit 2 Enable Parity for all digits 12 2 0 1 Odd or even parity Adjust the number of Hi output 0 0 Odd CMOS Even open collector 1 Even CMOS Odd open collector 13 2 0 1 POL OVF output logic 0 Data available at High CMOS or ON open collector 0 1 Data available at Low CMOS or OFF o...

Page 7: ...ay code to binary 0 Input Press ITEM or key until the display shows ITEM 22 Press DATA or key until the DATA display shows 1 0 100 Input Press ITEM or key until the display shows ITEM 23 Press DATA or key until the DATA display shows 5 0 Go to the MONITOR mode Press ITEM or key until the display shows ITEM 01 Press DATA or key until the display shows DATA 1 LOOP TEST OUTPUT The loop test output is...

Page 8: ...meter 3 Input Check that the input signal is within 0 100 of the full scale 4 Output Open collector Check that the output load is 30V DC 30mA at the maximum Saturation voltage is 1 1V DC Check the input threshold voltage at L level of the connected device to be greater than that CMOS level Check the output voltage H 4 5V DC L 0 5V DC LIGHTNING PROTECTION In order to protect the unit from lightning...

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